[PATCH] D98840: [RISCV] Lower scalable vector masked loads to intrinsics to match fixed vectors and reduce isel patterns.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 17 19:24:38 PDT 2021
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3222
+
+ return DAG.getMergeValues({Result, Chain}, DL);
}
----------------
There was a bug here. We were returning the old chain. Need to figure out why that didn't break anything. The fixed vector tests have a store following the load so that chain should have been alive.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D98840/new/
https://reviews.llvm.org/D98840
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