[llvm] 2416f24 - [M68k] Use fixed asm string for MxPseudo instructions

[Min-Yih Hsu via llvm-commits]

Author: Ricky Taylor
Date: 2021-03-17T13:31:27-07:00
New Revision: 2416f2436334450d216c7aa62a6624dc17765228

URL: https://github.com/llvm/llvm-project/commit/2416f2436334450d216c7aa62a6624dc17765228
DIFF: https://github.com/llvm/llvm-project/commit/2416f2436334450d216c7aa62a6624dc17765228.diff

LOG: [M68k] Use fixed asm string for MxPseudo instructions

This is required because empty strings are not allowed when generating
the assembly parser tables.

Differential Revision: https://reviews.llvm.org/D98532

Added: 
    

Modified: 
    llvm/lib/Target/M68k/M68kInstrCompiler.td
    llvm/lib/Target/M68k/M68kInstrControl.td
    llvm/lib/Target/M68k/M68kInstrData.td
    llvm/lib/Target/M68k/M68kInstrFormats.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/M68k/M68kInstrCompiler.td b/llvm/lib/Target/M68k/M68kInstrCompiler.td
index 4d1d20745158..bcb815dbc4eb 100644
--- a/llvm/lib/Target/M68k/M68kInstrCompiler.td
+++ b/llvm/lib/Target/M68k/M68kInstrCompiler.td
@@ -57,7 +57,6 @@ def : Pat<(i32 (MxWrapperPC tblockaddress :$src)), (LEA32q tblockaddress :$src)>
 let usesCustomInserter = 1, Uses = [CCR] in
 class MxCMove<MxType TYPE>
     : MxPseudo<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$t, TYPE.ROp:$f, i8imm:$cond),
-               "",
                [(set TYPE.VT:$dst,
                      (TYPE.VT (MxCmov TYPE.VT:$t, TYPE.VT:$f, imm:$cond, CCR)))]>;
 
@@ -78,11 +77,11 @@ def CMOV32r : MxCMove<MxType32r>;
 let Defs = [SP, CCR], Uses = [SP] in {
 
   def ADJCALLSTACKDOWN
-    : MxPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), "#ADJCALLSTACKDOWN",
+    : MxPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                [(MxCallSeqStart timm:$amt1, timm:$amt2)]>;
 
   def ADJCALLSTACKUP
-    : MxPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), "#ADJCALLSTACKUP",
+    : MxPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                [(MxCallSeqEnd timm:$amt1, timm:$amt2)]>;
 
 } // Defs
@@ -124,5 +123,4 @@ def : Pat<(MxTCRet (i32 texternalsym:$dst), imm:$adj),
 let Defs = [SP, CCR], Uses = [SP] in
 let usesCustomInserter = 1 in
 def SALLOCA : MxPseudo<(outs MxARD32:$dst), (ins MxARD32:$size),
-                       "# variable sized alloca for segmented stacks",
                        [(set iPTR:$dst, (MxSegAlloca iPTR:$size))]>;

diff  --git a/llvm/lib/Target/M68k/M68kInstrControl.td b/llvm/lib/Target/M68k/M68kInstrControl.td
index 567e6b0427fb..708474726861 100644
--- a/llvm/lib/Target/M68k/M68kInstrControl.td
+++ b/llvm/lib/Target/M68k/M68kInstrControl.td
@@ -264,7 +264,7 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
 def RTS : MxInst<(outs), (ins), "rts", [], MxEncFixed<0x4E75>>;
 
 let isCodeGenOnly = 1 in
-def RET : MxPseudo<(outs), (ins i32imm:$adj, variable_ops), "",
+def RET : MxPseudo<(outs), (ins i32imm:$adj, variable_ops),
                    [(MxRet timm:$adj)]>;
 } // isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1
 
@@ -277,11 +277,11 @@ let Uses = [CCR], Defs = [CCR], isPseudo = 1 in {
 // FIXME These are pseudo ops that should be replaced with Pat<> patterns.
 // However, Pat<> can't replicate the destination reg into the inputs of the
 // result.
-def SETCS_C8d : MxPseudo<(outs MxDRD8:$dst), (ins), "",
+def SETCS_C8d : MxPseudo<(outs MxDRD8:$dst), (ins),
                          [(set MxDRD8:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
-def SETCS_C16d : MxPseudo<(outs MxDRD16:$dst), (ins), "",
+def SETCS_C16d : MxPseudo<(outs MxDRD16:$dst), (ins),
                           [(set MxDRD16:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
-def SETCS_C32d : MxPseudo<(outs MxXRD32:$dst), (ins), "",
+def SETCS_C32d : MxPseudo<(outs MxXRD32:$dst), (ins),
                           [(set MxXRD32:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
 } // Uses = [CCR], Defs = [CCR], isPseudo = 1
 

diff  --git a/llvm/lib/Target/M68k/M68kInstrData.td b/llvm/lib/Target/M68k/M68kInstrData.td
index 74db3a3daca5..40b9e4a2a7fa 100644
--- a/llvm/lib/Target/M68k/M68kInstrData.td
+++ b/llvm/lib/Target/M68k/M68kInstrData.td
@@ -588,10 +588,10 @@ def POP32r : MxPseudo<(outs XR32:$reg), (ins)>;
 
 let Defs = [CCR] in {
 class MxPseudoMove_RR<MxType DST, MxType SRC, list<dag> PAT = []>
-    : MxPseudo<(outs DST.ROp:$dst), (ins SRC.ROp:$src), "", PAT>;
+    : MxPseudo<(outs DST.ROp:$dst), (ins SRC.ROp:$src), PAT>;
 
 class MxPseudoMove_RM<MxType DST, MxOperand SRCOpd, list<dag> PAT = []>
-    : MxPseudo<(outs DST.ROp:$dst), (ins SRCOpd:$src), "", PAT>;
+    : MxPseudo<(outs DST.ROp:$dst), (ins SRCOpd:$src), PAT>;
 }
 
 /// This group of Pseudos is analogues to the real x86 extending moves, but

diff  --git a/llvm/lib/Target/M68k/M68kInstrFormats.td b/llvm/lib/Target/M68k/M68kInstrFormats.td
index b00db4915df2..b147537eb32b 100644
--- a/llvm/lib/Target/M68k/M68kInstrFormats.td
+++ b/llvm/lib/Target/M68k/M68kInstrFormats.td
@@ -364,7 +364,7 @@ class MxInst<dag outs, dag ins,
 }
 
 // M68k PSEUDO INSTRUCTION
-class MxPseudo<dag outs, dag ins, string asmStr = "", list<dag> pattern = []>
-    : MxInst<outs, ins, asmStr, pattern> {
+class MxPseudo<dag outs, dag ins, list<dag> pattern = []>
+    : MxInst<outs, ins, "; error: this should not be emitted", pattern> {
   let isPseudo = 1;
 }