[PATCH] D98536: [M68k] Convert register Aliases to AltNames

[Min-Yih Hsu via Phabricator via llvm-commits]

myhsu added a comment.

In D98536#2630147 <https://reviews.llvm.org/D98536#2630147>, @ricky26 wrote:

> In D98536#2627583 <https://reviews.llvm.org/D98536#2627583>, @myhsu wrote:
>
>> Are you trying to distinguish the sub-register use cases from alternative naming (e.g. a5 & bp)?
>
> Kind of. I was running into a number of cases where I had to handle A7/SP separately (for example). I was worried this was eventually going to lead to significant code duplication and/or errors. `AltNames` seemed to make the most sense. SP/etc are really only used to make assembly more readable. (For that reason, I actually made SP the default rendering of A7.)

That make sense. I only have few syntax comments inlined below.



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Comment at: llvm/lib/Target/M68k/M68kRegisterInfo.td:94
 // Address Registers
-def AR16 : MxRegClass<[i16], 16, (sequence "WA%u", 0, 6)>;
-def AR32 : MxRegClass<[i32], 32, (add (sequence "A%u", 0, 6), SP)>;
+def AR16 : MxRegClass<[i16], 16, (add WA0, WA1, WA2, WA3, WA4, WA5, WA6, WSP)>;
+def AR32 : MxRegClass<[i32], 32, (add A0, A1, A2, A3, A4, A5, A6, SP)>;
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Is there any reason to expand these registers rather than using the original syntax (i.e. using `sequence`)?


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Comment at: llvm/lib/Target/M68k/M68kRegisterInfo.td:127
+def SPILL   : MxRegClass<[i32], 32, (add XR32)>;
+def SPILL_R : MxRegClass<[i32], 32, (add SP, A6, A5, A4, A3, A2, A1, A0, D7, D6, D5, D4, D3, D2, D1, D0)>;
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ditto the same question above


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