[PATCH] D98604: [MCA] Ensure that writes occur in-order

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb accepted this revision.
andreadb added a comment.
This revision is now accepted and ready to land.

LGTM.

Thanks a lot Andrew.

P.s.: once this is committed, we can resume the review on the other patch.

-Andrea

> Although this part is a bit problematic: "Subsequent instructions are allowed to
> issue, execute, and retire, provided they do not depend on the result of the
> VDIV, or VSQRT, and they are not VDIV or VSQRT themselves". MCA does not handle
> this, but this should never happen (at least for A55), because the FDIV/VSQRT
> instructions go through the same FP-pipeline, and take ResourceCycles
> according to their latency.

Yeah. This problem has to do with the presence of non-pipelined execution units. On Intel and AMD too, the divider is non-pipelined. So, when a division is issued, the divider gets busy (and therefore unavailable) for a given number of cycles, until the division terminates. As you wrote, the way how people normally address "issues" related to non-pipelined resources is by tweaking resource cycle consumptions in in the scheduling model.


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https://reviews.llvm.org/D98604