[PATCH] D98690: [AArch64][SVE] Test more types in sve-fixed-length-subvector.ll

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll:50
+; CHECK-LABEL: subvector_v16i16:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl16
+; VBITS_GE_512: ld1h { [[DATA:z[0-9]+.h]] }, [[PG]]/z, [x0]
----------------
Should this just be a normal CHECK line consistent with the v8i32 case (same size as v16i16)?


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll:64
+; CHECK-LABEL: subvector_v32i16:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl32
+; VBITS_GE_1024: ld1h { [[DATA:z[0-9]+.h]] }, [[PG]]/z, [x0]
----------------
VBITS_GE_512 consistent with the v16i32 case?


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll:78
+; CHECK-LABEL: subvector_v64i16:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl64
+; VBITS_GE_2048: ld1h { [[DATA:z[0-9]+.h]] }, [[PG]]/z, [x0]
----------------
VBITS_GE_1024?


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll:202
+
+define void @subvector_v16f16(<16 x half> *%in, <16 x half>* %out) #0 {
+; CHECK-LABEL: subvector_v16f16:
----------------
Same comments as the v16i16 and other cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98690/new/

https://reviews.llvm.org/D98690