[PATCH] D90853: [RISCV] Add DAG nodes to represent read/write CSR

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D90853#2629528 <https://reviews.llvm.org/D90853#2629528>, @sepavloff wrote:

> In D90853#2625350 <https://reviews.llvm.org/D90853#2625350>, @craig.topper wrote:
>
>> In D90853#2625329 <https://reviews.llvm.org/D90853#2625329>, @sepavloff wrote:
>>
>>> My point is that:
>>>
>>> - Using X0 as destination is an encoding trick to save opcode space, there is no sense to expose it to higher levels, like DAG or MIR.
>>> - Machine instruction or DAG node which have X0 as destination register breaks DAG or MIR design, as such instruction actually is not a definitions for X0.
>>
>> AArch64 has a pass that replaces defs with X0, AArch64DeadRegisterDefinitionsPass. This is how a subtract becomes a compare. So it is not unprecedented.
>
> Interesting pass. Thank you for the reference.
>
> It sets `xzr` as destination and marks it as dead. The pass is executed relatively late, just before register allocator. Probably RISC-V could use similar technique.
>
> In D90853#2625350 <https://reviews.llvm.org/D90853#2625350>, @craig.topper wrote:
>
>> In order to model set rounding mode, don't we need the write_csr pseudo instruction to have an implicit def of FRMReg?
>
> There are many system registers, putting them all to implicit definitions of `write_csr` does not look a flexible solution. I think about setting implicit definitions manually, using `addOperand` somewhere after selection.

Or we have a pseudo instruction per system register that we care about updating. It's also possible we want to add scheduling information for writing specific CSRs.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90853/new/

https://reviews.llvm.org/D90853