[PATCH] D98706: [SCEV] Add false->any implication to save compile time

[Max Kazantsev via Phabricator via llvm-commits]

mkazantsev created this revision.
mkazantsev added reviewers: lebedev.ri, nikic, reames.
Herald added subscribers: javed.absar, hiraditya.
mkazantsev requested review of this revision.
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Formal logic says that `false` may imply anything. We can save some compile
time in SCEV, saying that any predicate is true whenever we try to imply it
by a constant false condition. Hopefully this should reduce the total dominator
traversal time and make implication queries cheaper.


https://reviews.llvm.org/D98706

Files:
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
  llvm/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll
  llvm/test/Transforms/IndVarSimplify/X86/pr35406.ll
  llvm/test/Transforms/IndVarSimplify/trivial-guard.ll

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