[llvm] 9575c48 - [AArch64][GlobalISel] Fix crash on lowering <1 x half> types.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2021-03-15T23:27:43-07:00
New Revision: 9575c48b8959dae3c3e39e0227435ae6ebd71443

URL: https://github.com/llvm/llvm-project/commit/9575c48b8959dae3c3e39e0227435ae6ebd71443
DIFF: https://github.com/llvm/llvm-project/commit/9575c48b8959dae3c3e39e0227435ae6ebd71443.diff

LOG: [AArch64][GlobalISel] Fix crash on lowering <1 x half> types.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index d16e2fd13475..dbe5f5635048 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -357,9 +357,14 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
               return false;
             }
           } else {
-            // A scalar extend.
-            CurVReg =
-                MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}).getReg(0);
+            // If the split EVT was a <1 x T> vector, and NewVT is T, then we
+            // don't have to do anything since we don't distinguish between the
+            // two.
+            if (NewLLT != MRI.getType(CurVReg)) {
+              // A scalar extend.
+              CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
+                            .getReg(0);
+            }
           }
         }
       }

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
index ee73e58798c7..f34f0981c211 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
@@ -31,3 +31,16 @@ define i24 @test_v3i8(<3 x i8> %a) {
   ret i24 %res
 }
 
+
+define <1 x half> @test_v1s16(<1 x float> %x) {
+  ; CHECK-LABEL: name: test_v1s16
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   liveins: $d0
+  ; CHECK:   [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+  ; CHECK:   [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[UV]](s32)
+  ; CHECK:   $h0 = COPY [[FPTRUNC]](s16)
+  ; CHECK:   RET_ReallyLR implicit $h0
+  %tmp = fptrunc <1 x float> %x to <1 x half>
+  ret <1 x half> %tmp
+}