[PATCH] D98629: [RISCV] Spilling for Zvlsseg registers.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:226
+      // will be used when expanding these pseudo instructions.
+      MIB.addReg(RISCV::X0).addImm(0).addImm(0);
+    }
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Why do we need these fields as immediates if they are already part of the opcode name? Can't we just use the switch in isRVVSpillForZvlsseg to look them up anytime we need them?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D98629/new/

https://reviews.llvm.org/D98629