[llvm] 5d44c92 - Change void getNoop(MCInst &NopInst) to MCInst getNop()
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 15 12:05:40 PDT 2021
Author: Fangrui Song
Date: 2021-03-15T12:05:34-07:00
New Revision: 5d44c92bf82b7b1055a5a9826695b21eaa43530c
URL: https://github.com/llvm/llvm-project/commit/5d44c92bf82b7b1055a5a9826695b21eaa43530c
DIFF: https://github.com/llvm/llvm-project/commit/5d44c92bf82b7b1055a5a9826695b21eaa43530c.diff
LOG: Change void getNoop(MCInst &NopInst) to MCInst getNop()
Prefer (self-documenting) return values to output parameters (which are
liable to be used).
While here, rename Noop to Nop which is more widely used and improves
consistency with hasEmitNops/setEmitNops/emitNop/etc.
Added:
Modified:
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/BasicBlockSections.cpp
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.h
llvm/lib/Target/ARM/ARMInstrInfo.cpp
llvm/lib/Target/ARM/ARMInstrInfo.h
llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
llvm/lib/Target/ARM/Thumb1InstrInfo.h
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/lib/Target/ARM/Thumb2InstrInfo.h
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index a7d5c2e6059f..e603e69a50ba 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1395,7 +1395,7 @@ class TargetInstrInfo : public MCInstrInfo {
unsigned Quantity) const;
/// Return the noop instruction to use for a noop.
- virtual void getNoop(MCInst &NopInst) const;
+ virtual MCInst getNop() const;
/// Return true for post-incremented instructions.
virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index d55747691ec5..fc0b278325d9 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -1363,8 +1363,7 @@ void AsmPrinter::emitFunctionBody() {
const Triple &TT = TM.getTargetTriple();
if (!HasAnyRealCode && (MAI->hasSubsectionsViaSymbols() ||
(TT.isOSWindows() && TT.isOSBinFormatCOFF()))) {
- MCInst Noop;
- MF->getSubtarget().getInstrInfo()->getNoop(Noop);
+ MCInst Noop = MF->getSubtarget().getInstrInfo()->getNop();
// Targets can opt-out of emitting the noop here by leaving the opcode
// unspecified.
@@ -3003,8 +3002,7 @@ void AsmPrinter::printOffset(int64_t Offset, raw_ostream &OS) const {
}
void AsmPrinter::emitNops(unsigned N) {
- MCInst Nop;
- MF->getSubtarget().getInstrInfo()->getNoop(Nop);
+ MCInst Nop = MF->getSubtarget().getInstrInfo()->getNop();
for (; N; --N)
EmitToStreamer(*OutStreamer, Nop);
}
diff --git a/llvm/lib/CodeGen/BasicBlockSections.cpp b/llvm/lib/CodeGen/BasicBlockSections.cpp
index 307bfae42519..1a6eed272ca2 100644
--- a/llvm/lib/CodeGen/BasicBlockSections.cpp
+++ b/llvm/lib/CodeGen/BasicBlockSections.cpp
@@ -309,10 +309,9 @@ static bool avoidZeroOffsetLandingPad(MachineFunction &MF) {
MachineBasicBlock::iterator MI = MBB.begin();
while (!MI->isEHLabel())
++MI;
- MCInst Noop;
- MF.getSubtarget().getInstrInfo()->getNoop(Noop);
+ MCInst Nop = MF.getSubtarget().getInstrInfo()->getNop();
BuildMI(MBB, MI, DebugLoc(),
- MF.getSubtarget().getInstrInfo()->get(Noop.getOpcode()));
+ MF.getSubtarget().getInstrInfo()->get(Nop.getOpcode()));
return false;
}
}
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 165860ef1aa8..320a013a864d 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -472,9 +472,7 @@ static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI,
return nullptr;
}
-void TargetInstrInfo::getNoop(MCInst &NopInst) const {
- llvm_unreachable("Not implemented");
-}
+MCInst TargetInstrInfo::getNop() const { llvm_unreachable("Not implemented"); }
static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr &MI,
ArrayRef<unsigned> Ops, int FrameIndex,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 6fd0dc58a470..64adc973beeb 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -35,6 +35,7 @@
#include "llvm/IR/GlobalValue.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
@@ -4054,9 +4055,8 @@ bool llvm::rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
return false;
}
-void AArch64InstrInfo::getNoop(MCInst &NopInst) const {
- NopInst.setOpcode(AArch64::HINT);
- NopInst.addOperand(MCOperand::createImm(0));
+MCInst AArch64InstrInfo::getNop() const {
+ return MCInstBuilder(AArch64::HINT).addImm(0);
}
// AArch64 supports MachineCombiner.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index ed38dda208c8..8a724d1a1fee 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -209,7 +209,7 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
const DebugLoc &DL, Register DstReg,
ArrayRef<MachineOperand> Cond, Register TrueReg,
Register FalseReg) const override;
- void getNoop(MCInst &NopInst) const override;
+ MCInst getNop() const override;
bool isSchedulingBoundary(const MachineInstr &MI,
const MachineBasicBlock *MBB,
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index 2790ac215f86..3c6c6960b80f 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -32,7 +32,8 @@ ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
: ARMBaseInstrInfo(STI), RI() {}
/// Return the noop instruction to use for a noop.
-void ARMInstrInfo::getNoop(MCInst &NopInst) const {
+MCInst ARMInstrInfo::getNop() const {
+ MCInst NopInst;
if (hasNOP()) {
NopInst.setOpcode(ARM::HINT);
NopInst.addOperand(MCOperand::createImm(0));
@@ -46,6 +47,7 @@ void ARMInstrInfo::getNoop(MCInst &NopInst) const {
NopInst.addOperand(MCOperand::createReg(0));
NopInst.addOperand(MCOperand::createReg(0));
}
+ return NopInst;
}
unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.h b/llvm/lib/Target/ARM/ARMInstrInfo.h
index 042b53f0f8c3..178d7a2c630e 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.h
@@ -25,7 +25,7 @@ class ARMInstrInfo : public ARMBaseInstrInfo {
explicit ARMInstrInfo(const ARMSubtarget &STI);
/// Return the noop instruction to use for a noop.
- void getNoop(MCInst &NopInst) const override;
+ MCInst getNop() const override;
// Return the non-pre/post incrementing version of 'Opc'. Return 0
// if there is not such an opcode.
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index 79afa378cb62..cf5eb4b4c0f1 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -16,6 +16,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstBuilder.h"
using namespace llvm;
@@ -23,12 +24,12 @@ Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
: ARMBaseInstrInfo(STI), RI() {}
/// Return the noop instruction to use for a noop.
-void Thumb1InstrInfo::getNoop(MCInst &NopInst) const {
- NopInst.setOpcode(ARM::tMOVr);
- NopInst.addOperand(MCOperand::createReg(ARM::R8));
- NopInst.addOperand(MCOperand::createReg(ARM::R8));
- NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
- NopInst.addOperand(MCOperand::createReg(0));
+MCInst Thumb1InstrInfo::getNop() const {
+ return MCInstBuilder(ARM::tMOVr)
+ .addReg(ARM::R8)
+ .addReg(ARM::R8)
+ .addImm(ARMCC::AL)
+ .addReg(0);
}
unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
index 017b7222337c..0b8f3ae7c776 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
@@ -25,7 +25,7 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
explicit Thumb1InstrInfo(const ARMSubtarget &STI);
/// Return the noop instruction to use for a noop.
- void getNoop(MCInst &NopInst) const override;
+ MCInst getNop() const override;
// Return the non-pre/post incrementing version of 'Opc'. Return 0
// if there is not such an opcode.
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index d728572e2858..5204e3b03e9e 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -25,6 +25,7 @@
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
@@ -48,11 +49,8 @@ Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
: ARMBaseInstrInfo(STI) {}
/// Return the noop instruction to use for a noop.
-void Thumb2InstrInfo::getNoop(MCInst &NopInst) const {
- NopInst.setOpcode(ARM::tHINT);
- NopInst.addOperand(MCOperand::createImm(0));
- NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
- NopInst.addOperand(MCOperand::createReg(0));
+MCInst Thumb2InstrInfo::getNop() const {
+ return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0);
}
unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
index 808167bfdcbc..e6d51796ba4d 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
@@ -26,7 +26,7 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
explicit Thumb2InstrInfo(const ARMSubtarget &STI);
/// Return the noop instruction to use for a noop.
- void getNoop(MCInst &NopInst) const override;
+ MCInst getNop() const override;
// Return the non-pre/post incrementing version of 'Opc'. Return 0
// if there is not such an opcode.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 7d2bd7c6947d..4d0595689d9e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1258,8 +1258,10 @@ void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
}
/// Return the noop instruction to use for a noop.
-void PPCInstrInfo::getNoop(MCInst &NopInst) const {
- NopInst.setOpcode(PPC::NOP);
+MCInst PPCInstrInfo::getNop() const {
+ MCInst Nop;
+ Nop.setOpcode(PPC::NOP);
+ return Nop;
}
// Branch analysis.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index c6ef1742b722..cbd5e4308fc3 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -559,7 +559,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
///
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
- void getNoop(MCInst &NopInst) const override;
+ MCInst getNop() const override;
std::pair<unsigned, unsigned>
decomposeMachineOperandsTargetFlags(unsigned TF) const override;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 2b8ef4d9347e..1354befbedd6 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -7709,8 +7709,10 @@ void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
}
/// Return the noop instruction to use for a noop.
-void X86InstrInfo::getNoop(MCInst &NopInst) const {
- NopInst.setOpcode(X86::NOOP);
+MCInst X86InstrInfo::getNop() const {
+ MCInst Nop;
+ Nop.setOpcode(X86::NOOP);
+ return Nop;
}
bool X86InstrInfo::isHighLatencyDef(int opc) const {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index d7d2370c6f67..3cf6a7c15ec8 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -439,7 +439,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
int64_t Offset2,
unsigned NumLoads) const override;
- void getNoop(MCInst &NopInst) const override;
+ MCInst getNop() const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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