[llvm] 018e96f - [RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)

[Craig Topper via llvm-commits]

Author: Philipp Tomsich
Date: 2021-03-15T11:32:43-07:00
New Revision: 018e96f71ff2d1617aff1ed1abd9c8ad61faf87d

URL: https://github.com/llvm/llvm-project/commit/018e96f71ff2d1617aff1ed1abd9c8ad61faf87d
DIFF: https://github.com/llvm/llvm-project/commit/018e96f71ff2d1617aff1ed1abd9c8ad61faf87d.diff

LOG: [RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)

The following code-sequence showed up in a testcase (isolated from
SPEC2017) for if-conversion and vectorization when searching for the
maximum in an array:
        addi    a2, zero, 1
        blt     a1, a2, .LBB0_5
which can be expressed as `bge zero,a1,.LBB0_5`/`blez a1,/LBB0_5`.

More generally, we want to express (a < 1) as (a <= 0).

This adds the required isel-pattern and updates the testcases.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D98449

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td
    llvm/test/CodeGen/RISCV/branch.ll
    llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index ae9167098a13..6e093c1c9022 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -996,6 +996,9 @@ def : Pat<(brcond (XLenVT (xor GPR:$cond, 1)), bb:$imm12),
 // Match X > -1, the canonical form of X >= 0, to the bgez pattern.
 def : Pat<(brcond (XLenVT (setgt GPR:$rs1, -1)), bb:$imm12),
           (BGE GPR:$rs1, X0, bb:$imm12)>;
+// Lower (a < 1) as (0 >= a) into the blez pattern.
+def : Pat<(brcond (XLenVT (setlt GPR:$lhs, 1)), bb:$imm12),
+          (BGE X0, GPR:$lhs, bb:$imm12)>;
 
 let isBarrier = 1, isBranch = 1, isTerminator = 1 in
 def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,

diff  --git a/llvm/test/CodeGen/RISCV/branch.ll b/llvm/test/CodeGen/RISCV/branch.ll
index 065c00bbb279..dca90d9e889a 100644
--- a/llvm/test/CodeGen/RISCV/branch.ll
+++ b/llvm/test/CodeGen/RISCV/branch.ll
@@ -6,44 +6,47 @@ define void @foo(i32 %a, i32 *%b, i1 %c) nounwind {
 ; RV32I-LABEL: foo:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    beq a3, a0, .LBB0_13
+; RV32I-NEXT:    beq a3, a0, .LBB0_14
 ; RV32I-NEXT:  # %bb.1: # %test2
 ; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bne a3, a0, .LBB0_13
+; RV32I-NEXT:    bne a3, a0, .LBB0_14
 ; RV32I-NEXT:  # %bb.2: # %test3
 ; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    blt a3, a0, .LBB0_13
+; RV32I-NEXT:    blt a3, a0, .LBB0_14
 ; RV32I-NEXT:  # %bb.3: # %test4
 ; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bge a3, a0, .LBB0_13
+; RV32I-NEXT:    bge a3, a0, .LBB0_14
 ; RV32I-NEXT:  # %bb.4: # %test5
 ; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bltu a3, a0, .LBB0_13
+; RV32I-NEXT:    bltu a3, a0, .LBB0_14
 ; RV32I-NEXT:  # %bb.5: # %test6
 ; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bgeu a3, a0, .LBB0_13
+; RV32I-NEXT:    bgeu a3, a0, .LBB0_14
 ; RV32I-NEXT:  # %bb.6: # %test7
 ; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    blt a0, a3, .LBB0_13
+; RV32I-NEXT:    blt a0, a3, .LBB0_14
 ; RV32I-NEXT:  # %bb.7: # %test8
 ; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bge a0, a3, .LBB0_13
+; RV32I-NEXT:    bge a0, a3, .LBB0_14
 ; RV32I-NEXT:  # %bb.8: # %test9
 ; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bltu a0, a3, .LBB0_13
+; RV32I-NEXT:    bltu a0, a3, .LBB0_14
 ; RV32I-NEXT:  # %bb.9: # %test10
 ; RV32I-NEXT:    lw a3, 0(a1)
-; RV32I-NEXT:    bgeu a0, a3, .LBB0_13
+; RV32I-NEXT:    bgeu a0, a3, .LBB0_14
 ; RV32I-NEXT:  # %bb.10: # %test11
 ; RV32I-NEXT:    lw a0, 0(a1)
 ; RV32I-NEXT:    andi a0, a2, 1
-; RV32I-NEXT:    bnez a0, .LBB0_13
+; RV32I-NEXT:    bnez a0, .LBB0_14
 ; RV32I-NEXT:  # %bb.11: # %test12
 ; RV32I-NEXT:    lw a0, 0(a1)
-; RV32I-NEXT:    bgez a0, .LBB0_13
+; RV32I-NEXT:    bgez a0, .LBB0_14
 ; RV32I-NEXT:  # %bb.12: # %test13
 ; RV32I-NEXT:    lw a0, 0(a1)
-; RV32I-NEXT:  .LBB0_13: # %end
+; RV32I-NEXT:    blez a0, .LBB0_14
+; RV32I-NEXT:  # %bb.13: # %test14
+; RV32I-NEXT:    lw a0, 0(a1)
+; RV32I-NEXT:  .LBB0_14: # %end
 ; RV32I-NEXT:    ret
   %val1 = load volatile i32, i32* %b
   %tst1 = icmp eq i32 %val1, %a
@@ -110,8 +113,15 @@ test12:
   %tst12 = icmp sgt i32 %val12, -1
   br i1 %tst12, label %end, label %test13
 
+; Check that we use blez (X <= 0) for (X < 1)
+
 test13:
   %val13 = load volatile i32, i32* %b
+  %tst13 = icmp slt i32 %val13, 1
+  br i1 %tst13, label %end, label %test14
+
+test14:
+  %val14 = load volatile i32, i32* %b
   br label %end
 
 end:

diff  --git a/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll b/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
index 38cac4d77066..fbfa7ce9dbb3 100644
--- a/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
+++ b/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
@@ -29,8 +29,7 @@ define dso_local void @control_flow_with_mem_access() local_unnamed_addr nounwin
 ; CHECK-NEXT:    lui a0, %hi(s)
 ; CHECK-NEXT:    addi a0, a0, %lo(s)
 ; CHECK-NEXT:    lw a1, 164(a0)
-; CHECK-NEXT:    addi a2, zero, 1
-; CHECK-NEXT:    blt a1, a2, .LBB1_2
+; CHECK-NEXT:    blez a1, .LBB1_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    addi a1, zero, 10
 ; CHECK-NEXT:    sw a1, 160(a0)