[PATCH] D98628: [MCA] Disable RCU for InOrderIssueStage

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic created this revision.
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This is a follow-up for:
D98604 <https://reviews.llvm.org/D98604> [MCA] Ensure that writes occur in-order

When instructions are aligned by the order of writes, they retire
in-order naturally. There is no need for an RCU, so it is disabled.
RCU statistic is adjusted to handle this.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98628

Files:
  llvm/include/llvm/MCA/HWEventListener.h
  llvm/include/llvm/MCA/HardwareUnits/RetireControlUnit.h
  llvm/include/llvm/MCA/Stages/DispatchStage.h
  llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
  llvm/include/llvm/MCA/Stages/RetireStage.h
  llvm/lib/MCA/Context.cpp
  llvm/lib/MCA/Stages/DispatchStage.cpp
  llvm/lib/MCA/Stages/InOrderIssueStage.cpp
  llvm/lib/MCA/Stages/RetireStage.cpp
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s
  llvm/tools/llvm-mca/Views/RetireControlUnitStatistics.cpp

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