[PATCH] D87465: [TargetLowering] Change SimplifyDemandedBits for XOR

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1367
+        // when all demanded bits of Y and Z are known to be different
+        if (Op0.getOpcode() == ISD::OR &&
+            DemandedBits.isSubsetOf(C->getAPIntValue() ^ C1->getAPIntValue()))
----------------
RKSimon wrote:
> ISD::AND ?
Good spot. Fixed. This patch no longer seems to improve anything (and I only wrote it in the first place to address some regressions in D87145, which has since been landed) so I guess I'll abandon it unless you have some particular interest in it?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87465/new/

https://reviews.llvm.org/D87465