[llvm] 70ee8dc - Fix MSVC "switch statement contains 'default' but no 'case' labels" warning. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-03-15T09:45:45Z
New Revision: 70ee8dc0b694c054606aabb49ff6c8c6e077f7e9

URL: https://github.com/llvm/llvm-project/commit/70ee8dc0b694c054606aabb49ff6c8c6e077f7e9
DIFF: https://github.com/llvm/llvm-project/commit/70ee8dc0b694c054606aabb49ff6c8c6e077f7e9.diff

LOG: Fix MSVC "switch statement contains 'default' but no 'case' labels" warning. NFCI.

Added: 
    

Modified: 
    llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp b/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
index f15d0d18edaa..8a0f32b58da4 100644
--- a/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
+++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
@@ -134,11 +134,8 @@ static unsigned getRelaxedOpcodeBranch(const MCInst &Inst) {
 
 static unsigned getRelaxedOpcodeArith(const MCInst &Inst) {
   unsigned Op = Inst.getOpcode();
-  switch (Op) {
-  default:
-    return Op;
-    // NOTE there will be some relaxations for PCD and ARD mem for x20
-  }
+  // NOTE there will be some relaxations for PCD and ARD mem for x20
+  return Op;
 }
 
 static unsigned getRelaxedOpcode(const MCInst &Inst) {