[llvm] 0ddd537 - [Test] Replace checks with auto-generated checks
Max Kazantsev via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 15 00:33:33 PDT 2021
Author: Max Kazantsev
Date: 2021-03-15T14:32:00+07:00
New Revision: 0ddd5376058ac42c2ea1b1853ab4938698079edb
URL: https://github.com/llvm/llvm-project/commit/0ddd5376058ac42c2ea1b1853ab4938698079edb
DIFF: https://github.com/llvm/llvm-project/commit/0ddd5376058ac42c2ea1b1853ab4938698079edb.diff
LOG: [Test] Replace checks with auto-generated checks
Added:
Modified:
llvm/test/Transforms/JumpThreading/thread-loads.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/JumpThreading/thread-loads.ll b/llvm/test/Transforms/JumpThreading/thread-loads.ll
index fe3b276e7dd8..6d60e7303ad8 100644
--- a/llvm/test/Transforms/JumpThreading/thread-loads.ll
+++ b/llvm/test/Transforms/JumpThreading/thread-loads.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -jump-threading -S | FileCheck %s
; RUN: opt < %s -aa-pipeline=basic-aa -passes=jump-threading -S | FileCheck %s
@@ -8,33 +9,45 @@ target triple = "i386-apple-darwin7"
; rdar://6402033
define i32 @test1(i32* %P) nounwind {
; CHECK-LABEL: @test1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 (...) @f1() #[[ATTR0:[0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[BB1:%.*]], label [[BB1_THREAD:%.*]]
+; CHECK: bb1.thread:
+; CHECK-NEXT: store i32 42, i32* [[P:%.*]], align 4
+; CHECK-NEXT: br label [[BB3:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[DOTPR:%.*]] = load i32, i32* [[P]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOTPR]], 36
+; CHECK-NEXT: br i1 [[TMP2]], label [[BB3]], label [[BB2:%.*]]
+; CHECK: bb2:
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 (...) @f2() #[[ATTR0]]
+; CHECK-NEXT: ret i32 0
+; CHECK: bb3:
+; CHECK-NEXT: [[RES_02:%.*]] = phi i32 [ 1, [[BB1_THREAD]] ], [ 0, [[BB1]] ]
+; CHECK-NEXT: ret i32 [[RES_02]]
+;
entry:
- %0 = tail call i32 (...) @f1() nounwind ; <i32> [#uses=1]
- %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
- br i1 %1, label %bb1, label %bb
+ %0 = tail call i32 (...) @f1() nounwind ; <i32> [#uses=1]
+ %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %bb1, label %bb
bb: ; preds = %entry
-; CHECK: bb1.thread:
-; CHECK: store
-; CHECK: br label %bb3
- store i32 42, i32* %P, align 4
- br label %bb1
+ store i32 42, i32* %P, align 4
+ br label %bb1
bb1: ; preds = %entry, %bb
- %res.0 = phi i32 [ 1, %bb ], [ 0, %entry ] ; <i32> [#uses=2]
- %2 = load i32, i32* %P, align 4 ; <i32> [#uses=1]
- %3 = icmp sgt i32 %2, 36 ; <i1> [#uses=1]
- br i1 %3, label %bb3, label %bb2
+ %res.0 = phi i32 [ 1, %bb ], [ 0, %entry ] ; <i32> [#uses=2]
+ %2 = load i32, i32* %P, align 4 ; <i32> [#uses=1]
+ %3 = icmp sgt i32 %2, 36 ; <i1> [#uses=1]
+ br i1 %3, label %bb3, label %bb2
bb2: ; preds = %bb1
- %4 = tail call i32 (...) @f2() nounwind ; <i32> [#uses=0]
- ret i32 %res.0
+ %4 = tail call i32 (...) @f2() nounwind ; <i32> [#uses=0]
+ ret i32 %res.0
bb3: ; preds = %bb1
-; CHECK: bb3:
-; CHECK: %res.02 = phi i32 [ 1, %bb1.thread ], [ 0, %bb1 ]
-; CHECK: ret i32 %res.02
- ret i32 %res.0
+ ret i32 %res.0
}
declare i32 @f1(...)
@@ -47,33 +60,45 @@ declare i32 @f2(...)
define i32 @test2(i32* %P) nounwind {
; CHECK-LABEL: @test2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 (...) @f1() #[[ATTR0]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0
+; CHECK-NEXT: br i1 [[TMP1]], label [[BB1:%.*]], label [[BB1_THREAD:%.*]]
+; CHECK: bb1.thread:
+; CHECK-NEXT: store i32 42, i32* [[P:%.*]], align 4, !tbaa [[TBAA0:![0-9]+]]
+; CHECK-NEXT: br label [[BB3:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[DOTPR:%.*]] = load i32, i32* [[P]], align 4, !tbaa [[TBAA0]]
+; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[DOTPR]], 36
+; CHECK-NEXT: br i1 [[TMP2]], label [[BB3]], label [[BB2:%.*]]
+; CHECK: bb2:
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 (...) @f2() #[[ATTR0]]
+; CHECK-NEXT: ret i32 0
+; CHECK: bb3:
+; CHECK-NEXT: [[RES_02:%.*]] = phi i32 [ 1, [[BB1_THREAD]] ], [ 0, [[BB1]] ]
+; CHECK-NEXT: ret i32 [[RES_02]]
+;
entry:
- %0 = tail call i32 (...) @f1() nounwind ; <i32> [#uses=1]
- %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
- br i1 %1, label %bb1, label %bb
+ %0 = tail call i32 (...) @f1() nounwind ; <i32> [#uses=1]
+ %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %bb1, label %bb
bb: ; preds = %entry
-; CHECK: bb1.thread:
-; CHECK: store{{.*}}, !tbaa !0
-; CHECK: br label %bb3
- store i32 42, i32* %P, align 4, !tbaa !0
- br label %bb1
+ store i32 42, i32* %P, align 4, !tbaa !0
+ br label %bb1
bb1: ; preds = %entry, %bb
- %res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
- %2 = load i32, i32* %P, align 4, !tbaa !0
- %3 = icmp sgt i32 %2, 36
- br i1 %3, label %bb3, label %bb2
+ %res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
+ %2 = load i32, i32* %P, align 4, !tbaa !0
+ %3 = icmp sgt i32 %2, 36
+ br i1 %3, label %bb3, label %bb2
bb2: ; preds = %bb1
- %4 = tail call i32 (...) @f2() nounwind
- ret i32 %res.0
+ %4 = tail call i32 (...) @f2() nounwind
+ ret i32 %res.0
bb3: ; preds = %bb1
-; CHECK: bb3:
-; CHECK: %res.02 = phi i32 [ 1, %bb1.thread ], [ 0, %bb1 ]
-; CHECK: ret i32 %res.02
- ret i32 %res.0
+ ret i32 %res.0
}
define i32 @test3(i8** %x, i1 %f) {
@@ -82,12 +107,24 @@ define i32 @test3(i8** %x, i1 %f) {
; predecessor ends up with two entries in the PHI node and they must share
; a single cast.
; CHECK-LABEL: @test3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8** [[X:%.*]] to i32**
+; CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP0]], align 8
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to i8*
+; CHECK-NEXT: br i1 [[F:%.*]], label [[IF_END57:%.*]], label [[IF_END57]]
+; CHECK: if.end57:
+; CHECK-NEXT: [[TMP3:%.*]] = phi i8* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[TMP2]], [[ENTRY]] ]
+; CHECK-NEXT: [[TOBOOL59:%.*]] = icmp eq i8* [[TMP3]], null
+; CHECK-NEXT: br i1 [[TOBOOL59]], label [[RETURN:%.*]], label [[IF_THEN60:%.*]]
+; CHECK: if.then60:
+; CHECK-NEXT: ret i32 42
+; CHECK: return:
+; CHECK-NEXT: ret i32 13
+;
entry:
%0 = bitcast i8** %x to i32**
%1 = load i32*, i32** %0, align 8
br i1 %f, label %if.end57, label %if.then56
-; CHECK: %[[LOAD:.*]] = load i32*, i32**
-; CHECK: %[[CAST:.*]] = bitcast i32* %[[LOAD]] to i8*
if.then56:
br label %if.end57
@@ -96,9 +133,6 @@ if.end57:
%2 = load i8*, i8** %x, align 8
%tobool59 = icmp eq i8* %2, null
br i1 %tobool59, label %return, label %if.then60
-; CHECK: %[[PHI:.*]] = phi i8* [ %[[CAST]], %[[PRED:[^ ]+]] ], [ %[[CAST]], %[[PRED]] ]
-; CHECK-NEXT: %[[CMP:.*]] = icmp eq i8* %[[PHI]], null
-; CHECK-NEXT: br i1 %[[CMP]]
if.then60:
ret i32 42
@@ -109,22 +143,34 @@ return:
define i32 @test4(i32* %P) {
; CHECK-LABEL: @test4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[V0:%.*]] = tail call i32 (...) @f1()
+; CHECK-NEXT: [[V1:%.*]] = icmp eq i32 [[V0]], 0
+; CHECK-NEXT: br i1 [[V1]], label [[BB1:%.*]], label [[BB1_THREAD:%.*]]
+; CHECK: bb1.thread:
+; CHECK-NEXT: store atomic i32 42, i32* [[P:%.*]] unordered, align 4
+; CHECK-NEXT: br label [[BB3:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[V2_PR:%.*]] = load atomic i32, i32* [[P]] unordered, align 4
+; CHECK-NEXT: [[V3:%.*]] = icmp sgt i32 [[V2_PR]], 36
+; CHECK-NEXT: br i1 [[V3]], label [[BB3]], label [[BB2:%.*]]
+; CHECK: bb2:
+; CHECK-NEXT: [[V4:%.*]] = tail call i32 (...) @f2()
+; CHECK-NEXT: ret i32 0
+; CHECK: bb3:
+; CHECK-NEXT: [[RES_04:%.*]] = phi i32 [ 1, [[BB1_THREAD]] ], [ 0, [[BB1]] ]
+; CHECK-NEXT: ret i32 [[RES_04]]
+;
entry:
%v0 = tail call i32 (...) @f1()
%v1 = icmp eq i32 %v0, 0
br i1 %v1, label %bb1, label %bb
bb:
-; CHECK: bb1.thread:
-; CHECK: store atomic
-; CHECK: br label %bb3
store atomic i32 42, i32* %P unordered, align 4
br label %bb1
bb1:
-; CHECK: bb1:
-; CHECK-NOT: phi
-; CHECK: load atomic
%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
%v2 = load atomic i32, i32* %P unordered, align 4
%v3 = icmp sgt i32 %v2, 36
@@ -140,26 +186,35 @@ bb3:
define i32 @test5(i32* %P) {
; Negative test
-
; CHECK-LABEL: @test5(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[V0:%.*]] = tail call i32 (...) @f1()
+; CHECK-NEXT: [[V1:%.*]] = icmp eq i32 [[V0]], 0
+; CHECK-NEXT: br i1 [[V1]], label [[BB1:%.*]], label [[BB:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: store atomic i32 42, i32* [[P:%.*]] release, align 4
+; CHECK-NEXT: br label [[BB1]]
+; CHECK: bb1:
+; CHECK-NEXT: [[RES_0:%.*]] = phi i32 [ 1, [[BB]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[V2:%.*]] = load atomic i32, i32* [[P]] acquire, align 4
+; CHECK-NEXT: [[V3:%.*]] = icmp sgt i32 [[V2]], 36
+; CHECK-NEXT: br i1 [[V3]], label [[BB3:%.*]], label [[BB2:%.*]]
+; CHECK: bb2:
+; CHECK-NEXT: [[V4:%.*]] = tail call i32 (...) @f2()
+; CHECK-NEXT: ret i32 [[RES_0]]
+; CHECK: bb3:
+; CHECK-NEXT: ret i32 [[RES_0]]
+;
entry:
%v0 = tail call i32 (...) @f1()
%v1 = icmp eq i32 %v0, 0
br i1 %v1, label %bb1, label %bb
bb:
-; CHECK: bb:
-; CHECK-NEXT: store atomic i32 42, i32* %P release, align 4
-; CHECK-NEXT: br label %bb1
store atomic i32 42, i32* %P release, align 4
br label %bb1
bb1:
-; CHECK: bb1:
-; CHECK-NEXT: %res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
-; CHECK-NEXT: %v2 = load atomic i32, i32* %P acquire, align 4
-; CHECK-NEXT: %v3 = icmp sgt i32 %v2, 36
-; CHECK-NEXT: br i1 %v3, label %bb3, label %bb2
%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
%v2 = load atomic i32, i32* %P acquire, align 4
@@ -176,26 +231,35 @@ bb3:
define i32 @test6(i32* %P) {
; Negative test
-
; CHECK-LABEL: @test6(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[V0:%.*]] = tail call i32 (...) @f1()
+; CHECK-NEXT: [[V1:%.*]] = icmp eq i32 [[V0]], 0
+; CHECK-NEXT: br i1 [[V1]], label [[BB1:%.*]], label [[BB:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: store i32 42, i32* [[P:%.*]], align 4
+; CHECK-NEXT: br label [[BB1]]
+; CHECK: bb1:
+; CHECK-NEXT: [[RES_0:%.*]] = phi i32 [ 1, [[BB]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[V2:%.*]] = load atomic i32, i32* [[P]] acquire, align 4
+; CHECK-NEXT: [[V3:%.*]] = icmp sgt i32 [[V2]], 36
+; CHECK-NEXT: br i1 [[V3]], label [[BB3:%.*]], label [[BB2:%.*]]
+; CHECK: bb2:
+; CHECK-NEXT: [[V4:%.*]] = tail call i32 (...) @f2()
+; CHECK-NEXT: ret i32 [[RES_0]]
+; CHECK: bb3:
+; CHECK-NEXT: ret i32 [[RES_0]]
+;
entry:
%v0 = tail call i32 (...) @f1()
%v1 = icmp eq i32 %v0, 0
br i1 %v1, label %bb1, label %bb
bb:
-; CHECK: bb:
-; CHECK-NEXT: store i32 42, i32* %P
-; CHECK-NEXT: br label %bb1
store i32 42, i32* %P
br label %bb1
bb1:
-; CHECK: bb1:
-; CHECK-NEXT: %res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
-; CHECK-NEXT: %v2 = load atomic i32, i32* %P acquire, align 4
-; CHECK-NEXT: %v3 = icmp sgt i32 %v2, 36
-; CHECK-NEXT: br i1 %v3, label %bb3, label %bb2
%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
%v2 = load atomic i32, i32* %P acquire, align 4
@@ -212,26 +276,35 @@ bb3:
define i32 @test7(i32* %P) {
; Negative test
-
; CHECK-LABEL: @test7(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[V0:%.*]] = tail call i32 (...) @f1()
+; CHECK-NEXT: [[V1:%.*]] = icmp eq i32 [[V0]], 0
+; CHECK-NEXT: br i1 [[V1]], label [[BB1:%.*]], label [[BB:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[P:%.*]], align 4
+; CHECK-NEXT: br label [[BB1]]
+; CHECK: bb1:
+; CHECK-NEXT: [[RES_0:%.*]] = phi i32 [ 1, [[BB]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[V2:%.*]] = load atomic i32, i32* [[P]] acquire, align 4
+; CHECK-NEXT: [[V3:%.*]] = icmp sgt i32 [[V2]], 36
+; CHECK-NEXT: br i1 [[V3]], label [[BB3:%.*]], label [[BB2:%.*]]
+; CHECK: bb2:
+; CHECK-NEXT: [[V4:%.*]] = tail call i32 (...) @f2()
+; CHECK-NEXT: ret i32 [[RES_0]]
+; CHECK: bb3:
+; CHECK-NEXT: ret i32 [[RES_0]]
+;
entry:
%v0 = tail call i32 (...) @f1()
%v1 = icmp eq i32 %v0, 0
br i1 %v1, label %bb1, label %bb
bb:
-; CHECK: bb:
-; CHECK-NEXT: %val = load i32, i32* %P
-; CHECK-NEXT: br label %bb1
%val = load i32, i32* %P
br label %bb1
bb1:
-; CHECK: bb1:
-; CHECK-NEXT: %res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
-; CHECK-NEXT: %v2 = load atomic i32, i32* %P acquire, align 4
-; CHECK-NEXT: %v3 = icmp sgt i32 %v2, 36
-; CHECK-NEXT: br i1 %v3, label %bb3, label %bb2
%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
%v2 = load atomic i32, i32* %P acquire, align 4
@@ -251,10 +324,12 @@ bb3:
; branch.
define void @test8(i32*, i32*, i32*) {
; CHECK-LABEL: @test8(
-; CHECK: %a = load i32, i32* %0, align 4, !range ![[RANGE4:[0-9]+]]
-; CHECK-NEXT: store i32 %a
-; CHECK-NEXT: %xxx = tail call i32 (...) @f1()
-; CHECK-NEXT: ret void
+; CHECK-NEXT: ret2:
+; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[TMP0:%.*]], align 4, !range [[RNG4:![0-9]+]]
+; CHECK-NEXT: store i32 [[A]], i32* [[TMP1:%.*]], align 4
+; CHECK-NEXT: [[XXX:%.*]] = tail call i32 (...) @f1() #[[ATTR0]]
+; CHECK-NEXT: ret void
+;
%a = load i32, i32* %0, !tbaa !0, !range !4, !alias.scope !9, !noalias !10
%b = load i32, i32* %0, !range !5
store i32 %a, i32* %1
@@ -274,17 +349,32 @@ ret2:
; metadata to the newly inserted load.
define void @test9(i32*, i32*, i32*, i1 %c) {
; CHECK-LABEL: @test9(
+; CHECK-NEXT: br i1 [[C:%.*]], label [[D1:%.*]], label [[D2:%.*]]
+; CHECK: d1:
+; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[TMP0:%.*]], align 4
+; CHECK-NEXT: br label [[D3:%.*]]
+; CHECK: d2:
+; CHECK-NEXT: [[XXXX:%.*]] = tail call i32 (...) @f1() #[[ATTR0]]
+; CHECK-NEXT: [[B_PR:%.*]] = load i32, i32* [[TMP0]], align 4, !tbaa [[TBAA0]]
+; CHECK-NEXT: br label [[D3]]
+; CHECK: d3:
+; CHECK-NEXT: [[B:%.*]] = phi i32 [ [[B_PR]], [[D2]] ], [ [[A]], [[D1]] ]
+; CHECK-NEXT: [[P:%.*]] = phi i32 [ 1, [[D2]] ], [ [[A]], [[D1]] ]
+; CHECK-NEXT: store i32 [[P]], i32* [[TMP1:%.*]], align 4
+; CHECK-NEXT: [[C2:%.*]] = icmp eq i32 [[B]], 8
+; CHECK-NEXT: br i1 [[C2]], label [[RET1:%.*]], label [[RET2:%.*]]
+; CHECK: ret1:
+; CHECK-NEXT: ret void
+; CHECK: ret2:
+; CHECK-NEXT: [[XXX:%.*]] = tail call i32 (...) @f1() #[[ATTR0]]
+; CHECK-NEXT: ret void
+;
br i1 %c, label %d1, label %d2
-; CHECK: d1:
-; CHECK-NEXT: %a = load i32, i32* %0, align 4{{$}}
d1:
%a = load i32, i32* %0, !range !4, !alias.scope !9, !noalias !10
br label %d3
-; CHECK: d2:
-; CHECK-NEXT: %xxxx = tail call i32 (...) @f1()
-; CHECK-NEXT: %b.pr = load i32, i32* %0, align 4, !tbaa !0{{$}}
d2:
%xxxx = tail call i32 (...) @f1() nounwind
br label %d3
@@ -305,15 +395,29 @@ ret2:
}
define i32 @fn_noalias(i1 %c2,i64* noalias %P, i64* noalias %P2) {
-; CHECK-LABEL: @fn_noalias
-; CHECK-LABEL: cond1:
-; CHECK: %[[LD1:.*]] = load i64, i64* %P
-; CHECK: br i1 %c, label %[[THREAD:.*]], label %end
-; CHECK-LABEL: cond2:
-; CHECK: %[[LD2:.*]] = load i64, i64* %P
-; CHECK-LABEL: cond3:
-; CHECK: %[[PHI:.*]] = phi i64 [ %[[LD1]], %[[THREAD]] ], [ %[[LD2]], %cond2 ]
-; CHECK: call void @fn3(i64 %[[PHI]])
+; CHECK-LABEL: @fn_noalias(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[C2:%.*]], label [[COND2:%.*]], label [[COND1:%.*]]
+; CHECK: cond1:
+; CHECK-NEXT: [[L1:%.*]] = load i64, i64* [[P:%.*]], align 4
+; CHECK-NEXT: store i64 42, i64* [[P2:%.*]], align 4
+; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[L1]], 0
+; CHECK-NEXT: br i1 [[C]], label [[COND2_THREAD:%.*]], label [[END:%.*]]
+; CHECK: cond2.thread:
+; CHECK-NEXT: call void @fn2(i64 [[L1]])
+; CHECK-NEXT: br label [[COND3:%.*]]
+; CHECK: cond2:
+; CHECK-NEXT: [[L2_PR:%.*]] = load i64, i64* [[P]], align 4
+; CHECK-NEXT: call void @fn2(i64 [[L2_PR]])
+; CHECK-NEXT: [[C3:%.*]] = icmp eq i64 [[L2_PR]], 0
+; CHECK-NEXT: br i1 [[C3]], label [[COND3]], label [[END]]
+; CHECK: cond3:
+; CHECK-NEXT: [[L23:%.*]] = phi i64 [ [[L1]], [[COND2_THREAD]] ], [ [[L2_PR]], [[COND2]] ]
+; CHECK-NEXT: call void @fn3(i64 [[L23]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: ret i32 0
+;
entry:
br i1 %c2, label %cond2, label %cond1
@@ -347,17 +451,46 @@ end:
@last = internal unnamed_addr global [65 x i32*] zeroinitializer, align 8
@next_status = internal unnamed_addr global [65 x %struct.NEXT_MOVE] zeroinitializer, align 8
define fastcc i32 @Search(i64 %idxprom.i, i64 %idxprom.i89, i32 %c) {
-; CHECK-LABEL: @Search
-; CHECK-LABEL: sw.bb.i:
-; CHECK: %[[LD1:.*]] = load i32, i32* %arrayidx185, align 4
-; CHECK: %[[C1:.*]] = icmp eq i32 %[[LD1]], 0
-; CHECK: br i1 %[[C1]], label %sw.bb21.i.thread, label %if.then.i64
-; CHECK-LABEL: sw.bb21.i.thread:
-; CHECK: br label %[[THREAD_TO:.*]]
-; CHECK-LABEL: sw.bb21.i:
-; CHECK: %[[LD2:.*]] = load i32, i32* %arrayidx185, align 4
-; CHECK: %[[C2:.*]] = icmp eq i32 %[[LD2]], 0
-; CHECK:br i1 %[[C2]], label %[[THREAD_TO]], label %cleanup
+; CHECK-LABEL: @Search(
+; CHECK-NEXT: cond.true282:
+; CHECK-NEXT: [[ARRAYIDX185:%.*]] = getelementptr inbounds [65 x i32], [65 x i32]* @hash_move, i64 0, i64 [[IDXPROM_I:%.*]]
+; CHECK-NEXT: [[ARRAYIDX307:%.*]] = getelementptr inbounds [65 x i32], [65 x i32]* @current_move, i64 0, i64 [[IDXPROM_I]]
+; CHECK-NEXT: [[ARRAYIDX89:%.*]] = getelementptr inbounds [65 x i32*], [65 x i32*]* @last, i64 0, i64 [[IDXPROM_I]]
+; CHECK-NEXT: [[PHASE:%.*]] = getelementptr inbounds [65 x %struct.NEXT_MOVE], [65 x %struct.NEXT_MOVE]* @next_status, i64 0, i64 [[IDXPROM_I]], i32 0
+; CHECK-NEXT: switch i32 [[C:%.*]], label [[CLEANUP:%.*]] [
+; CHECK-NEXT: i32 1, label [[SW_BB_I:%.*]]
+; CHECK-NEXT: i32 0, label [[SW_BB21_I:%.*]]
+; CHECK-NEXT: ]
+; CHECK: sw.bb.i:
+; CHECK-NEXT: [[CALL_I62:%.*]] = call fastcc i32* @GenerateCheckEvasions()
+; CHECK-NEXT: store i32* [[CALL_I62]], i32** [[ARRAYIDX89]], align 8
+; CHECK-NEXT: [[L2:%.*]] = load i32, i32* [[ARRAYIDX185]], align 4
+; CHECK-NEXT: [[TOBOOL_I63:%.*]] = icmp eq i32 [[L2]], 0
+; CHECK-NEXT: br i1 [[TOBOOL_I63]], label [[SW_BB21_I_THREAD:%.*]], label [[IF_THEN_I64:%.*]]
+; CHECK: sw.bb21.i.thread:
+; CHECK-NEXT: store i32 10, i32* [[PHASE]], align 8
+; CHECK-NEXT: br label [[DO_BODY_PREHEADER_I67:%.*]]
+; CHECK: if.then.i64:
+; CHECK-NEXT: store i32 7, i32* [[PHASE]], align 8
+; CHECK-NEXT: store i32 [[L2]], i32* [[ARRAYIDX307]], align 4
+; CHECK-NEXT: [[CALL16_I:%.*]] = call fastcc i32 @ValidMove(i32 [[L2]])
+; CHECK-NEXT: [[TOBOOL17_I:%.*]] = icmp eq i32 [[CALL16_I]], 0
+; CHECK-NEXT: br i1 [[TOBOOL17_I]], label [[IF_ELSE_I65:%.*]], label [[CLEANUP]]
+; CHECK: if.else.i65:
+; CHECK-NEXT: call void @f65()
+; CHECK-NEXT: br label [[SW_BB21_I]]
+; CHECK: sw.bb21.i:
+; CHECK-NEXT: [[L3_PR:%.*]] = load i32, i32* [[ARRAYIDX185]], align 4
+; CHECK-NEXT: store i32 10, i32* [[PHASE]], align 8
+; CHECK-NEXT: [[TOBOOL27_I:%.*]] = icmp eq i32 [[L3_PR]], 0
+; CHECK-NEXT: br i1 [[TOBOOL27_I]], label [[DO_BODY_PREHEADER_I67]], label [[CLEANUP]]
+; CHECK: do.body.preheader.i67:
+; CHECK-NEXT: call void @f67()
+; CHECK-NEXT: ret i32 67
+; CHECK: cleanup:
+; CHECK-NEXT: call void @Cleanup()
+; CHECK-NEXT: ret i32 0
+;
entry:
%arrayidx185 = getelementptr inbounds [65 x i32], [65 x i32]* @hash_move, i64 0, i64 %idxprom.i
%arrayidx307 = getelementptr inbounds [65 x i32], [65 x i32]* @current_move, i64 0, i64 %idxprom.i
@@ -367,8 +500,8 @@ entry:
cond.true282:
switch i32 %c, label %sw.default.i [
- i32 1, label %sw.bb.i
- i32 0, label %sw.bb21.i
+ i32 1, label %sw.bb.i
+ i32 0, label %sw.bb21.i
]
sw.default.i:
@@ -414,18 +547,24 @@ declare void @Cleanup()
declare void @f65()
define i32 @fn_SinglePred(i1 %c2,i64* %P) {
-; CHECK-LABEL: @fn_SinglePred
-; CHECK-LABEL: entry:
-; CHECK: %[[L1:.*]] = load i64, i64* %P
-; CHECK: br i1 %c, label %cond3, label %cond1
-; CHECK-LABEL: cond2:
-; CHECK-NOT: load
-; CHECK: %[[PHI:.*]] = phi i64 [ %[[L1]], %cond1 ]
-; CHECK: call void @fn2(i64 %[[PHI]])
-; CHECK: br label %end
-; CHECK-LABEL: cond3:
-; CHECK: call void @fn2(i64 %l1)
-; CHECK: call void @fn3(i64 %l1)
+; CHECK-LABEL: @fn_SinglePred(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[L1:%.*]] = load i64, i64* [[P:%.*]], align 4
+; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[L1]], 0
+; CHECK-NEXT: br i1 [[C]], label [[COND3:%.*]], label [[COND1:%.*]]
+; CHECK: cond1:
+; CHECK-NEXT: br i1 [[C2:%.*]], label [[COND2:%.*]], label [[END:%.*]]
+; CHECK: cond2:
+; CHECK-NEXT: [[L2:%.*]] = phi i64 [ [[L1]], [[COND1]] ]
+; CHECK-NEXT: call void @fn2(i64 [[L2]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: cond3:
+; CHECK-NEXT: call void @fn2(i64 [[L1]])
+; CHECK-NEXT: call void @fn3(i64 [[L1]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: ret i32 0
+;
entry:
%l1 = load i64, i64* %P
@@ -450,18 +589,26 @@ end:
}
define i32 @fn_SinglePredMultihop(i1 %c1, i1 %c2,i64* %P) {
-; CHECK-LABEL: @fn_SinglePredMultihop
-; CHECK-LABEL: entry:
-; CHECK: %[[L1:.*]] = load i64, i64* %P
-; CHECK: br i1 %c0, label %cond3, label %cond0
-; CHECK-LABEL: cond2:
-; CHECK-NOT: load
-; CHECK: %[[PHI:.*]] = phi i64 [ %[[L1]], %cond1 ]
-; CHECK: call void @fn2(i64 %[[PHI]])
-; CHECK: br label %end
-; CHECK-LABEL: cond3:
-; CHECK: call void @fn2(i64 %l1)
-; CHECK: call void @fn3(i64 %l1)
+; CHECK-LABEL: @fn_SinglePredMultihop(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[L1:%.*]] = load i64, i64* [[P:%.*]], align 4
+; CHECK-NEXT: [[C0:%.*]] = icmp eq i64 [[L1]], 0
+; CHECK-NEXT: br i1 [[C0]], label [[COND3:%.*]], label [[COND0:%.*]]
+; CHECK: cond0:
+; CHECK-NEXT: br i1 [[C1:%.*]], label [[COND1:%.*]], label [[END:%.*]]
+; CHECK: cond1:
+; CHECK-NEXT: br i1 [[C2:%.*]], label [[COND2:%.*]], label [[END]]
+; CHECK: cond2:
+; CHECK-NEXT: [[L2:%.*]] = phi i64 [ [[L1]], [[COND1]] ]
+; CHECK-NEXT: call void @fn2(i64 [[L2]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: cond3:
+; CHECK-NEXT: call void @fn2(i64 [[L1]])
+; CHECK-NEXT: call void @fn3(i64 [[L1]])
+; CHECK-NEXT: br label [[END]]
+; CHECK: end:
+; CHECK-NEXT: ret i32 0
+;
entry:
%l1 = load i64, i64* %P
@@ -496,14 +643,22 @@ declare void @fn3(i64)
; merge fully redudant and then we can jump-thread the block with the
; store.
;
-; CHECK-LABEL: define i32 @phi_translate_partial_redundant_loads(i32 %0, i32* %1, i32* %2
-; CHECK: merge.thread:
-; CHECK: store
-; CHECK: br label %left_x
-;
-; CHECK: left_x:
-; CHECK-NEXT: ret i32 20
define i32 @phi_translate_partial_redundant_loads(i32, i32*, i32*) {
+; CHECK-LABEL: @phi_translate_partial_redundant_loads(
+; CHECK-NEXT: [[CMP0:%.*]] = icmp ne i32 [[TMP0:%.*]], 0
+; CHECK-NEXT: br i1 [[CMP0]], label [[MERGE_THREAD:%.*]], label [[MERGE:%.*]]
+; CHECK: merge.thread:
+; CHECK-NEXT: store i32 1, i32* [[TMP1:%.*]], align 4
+; CHECK-NEXT: br label [[LEFT_X:%.*]]
+; CHECK: merge:
+; CHECK-NEXT: [[NEWLOAD_PR:%.*]] = load i32, i32* [[TMP2:%.*]], align 4
+; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[NEWLOAD_PR]], 5
+; CHECK-NEXT: br i1 [[CMP1]], label [[LEFT_X]], label [[RIGHT_X:%.*]]
+; CHECK: left_x:
+; CHECK-NEXT: ret i32 20
+; CHECK: right_x:
+; CHECK-NEXT: ret i32 10
+;
%cmp0 = icmp ne i32 %0, 0
br i1 %cmp0, label %left, label %right
@@ -527,7 +682,8 @@ right_x:
ret i32 10
}
-; CHECK: ![[RANGE4]] = !{i32 0, i32 1}
+
+; CHECK: [[RNG4]] = !{i32 0, i32 1}
!0 = !{!3, !3, i64 0}
!1 = !{!"omnipotent char", !2}
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