[PATCH] D98549: [AMDGPU] Fix copyPhysReg to not produce unalined vgpr access

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:915-918
+  } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) && !RI.hasAGPRs(SrcRC) &&
+             (RC == RI.getVGPRClassForBitWidth(Size) &&
+              (RI.isSGPRClass(SrcRC) ||
+               SrcRC == RI.getVGPRClassForBitWidth(Size)))) {
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rampitec wrote:
> arsenm wrote:
> > This seems more complicated than it needs to be
> Suggestions?
I.e. I do not see an easy way to check an RC is aligned.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98549/new/

https://reviews.llvm.org/D98549