[PATCH] D98549: [AMDGPU] Fix copyPhysReg to not produce unalined vgpr access

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:879
+  const TargetRegisterClass *SrcRC = RI.getPhysRegClass(SrcReg);
+  if (RC->hasSuperClassEq(RI.getVGPR64Class()) &&
+      !RI.hasAGPRs(SrcRC) &&
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It would be easier to follow if you directly referred to the aligned class. getVGPR64Class will always return that anyway on the targets with the alignment requirement


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:915-918
+  } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) && !RI.hasAGPRs(SrcRC) &&
+             (RC == RI.getVGPRClassForBitWidth(Size) &&
+              (RI.isSGPRClass(SrcRC) ||
+               SrcRC == RI.getVGPRClassForBitWidth(Size)))) {
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This seems more complicated than it needs to be


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  https://reviews.llvm.org/D98549/new/

https://reviews.llvm.org/D98549