[PATCH] D90853: [RISCV] Add DAG nodes to represent read/write CSR

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D90853#2625329 <https://reviews.llvm.org/D90853#2625329>, @sepavloff wrote:

> Hi all,
>
> What is the destiny of this patch?
>
> My point is that:
>
> - Using X0 as destination is an encoding trick to save opcode space, there is no sense to expose it to higher levels, like DAG or MIR.
> - Machine instruction or DAG node which have X0 as destination register breaks DAG or MIR design, as such instruction actually is not a definitions for X0.

AArch64 has a pass that replaces defs with X0, AArch64DeadRegisterDefinitionsPass. This is how a subtract becomes a compare. So it is not unprecedented.

> It looks like there is no alternative to dedicated instructions for writes to CSRs.
>
> What do you think?

In order to model set rounding mode, don't we need the write_csr pseudo instruction to have an implicit def of FRMReg?


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