[PATCH] D98527: [M68k] Tidy up some bit shifting during code emission
Min-Yih Hsu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 14 11:54:45 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG84094fb4fd0b: [M68k] Tidy up some bit shifting during code emission (authored by ricky26, committed by myhsu).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D98527/new/
https://reviews.llvm.org/D98527
Files:
llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
Index: llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
+++ llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
@@ -162,13 +162,13 @@
unsigned Written = 0;
if (Reg) {
uint32_t Val = RI->getEncodingValue(RegNum);
- Buffer |= Val << Offset;
+ Buffer |= (Val & 7) << Offset;
Offset += 3;
Written += 3;
}
if (DA) {
- Buffer |= (char)M68kII::isAddressRegister(RegNum) << Offset;
+ Buffer |= (uint64_t)M68kII::isAddressRegister(RegNum) << Offset;
Written++;
}
@@ -179,13 +179,9 @@
uint64_t &Buffer, unsigned Offset) {
assert(Size + Offset <= 64 && isUIntN(Size, Val) && "Value does not fit");
- // Pad the instruction with zeros if any
- // FIXME Emit zeros in the padding, since there might be trash in the buffer.
- Size += Pad;
-
// Writing Value in host's endianness
- Buffer |= Val << Offset;
- return Size;
+ Buffer |= (Val & ((1ULL << Size) - 1)) << Offset;
+ return Size + Pad;
}
unsigned M68kMCCodeEmitter::encodeImm(unsigned ThisByte, uint8_t Bead,
@@ -316,8 +312,7 @@
return Size;
}
- return EmitConstant(Imm & (UINT64_MAX >> (64 - Size)), Size, Pad, Buffer,
- Offset);
+ return EmitConstant(Imm & ((1ULL << Size) - 1), Size, Pad, Buffer, Offset);
}
#include "M68kGenMCCodeBeads.inc"
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