[PATCH] D98604: [MCA] Ensure that writes occur in-order

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic created this revision.
asavonic added reviewers: andreadb, dmgreen, evgeny777.
Herald added subscribers: gbedwell, hiraditya.
asavonic requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Delay the issue of a new instruction if that leads to out-of-order
commits of writes. With this change instructions are retired in-order
without RetireControlUnit, so it is disabled in InOrderIssueStage.

This patch fixes the problem described in:
https://bugs.llvm.org/show_bug.cgi?id=41796#c3


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98604

Files:
  llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
  llvm/lib/MCA/Stages/InOrderIssueStage.cpp
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s

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