[PATCH] D98567: [RISCV] Look through copies when trying to find an implicit def in addVSetVL.

[Craig Topper via Phabricator via llvm-commits]

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The InstrEmitter can sometimes insert a copy after an IMPLICIT_DEF
before connecting it to the vector instruction. This occurs when
constrainRegClass reduces to a class with less than 4 registers.
I believe LMUL8 on masked instructions triggers this since the
result can only use the v8, v16, or v24 register group as the mask
is using v0.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98567

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
  llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll

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