[PATCH] D98491: [AMDGPU] Split GCN subtarget features for unaligned access

[Mirko Brkusanin via Phabricator via llvm-commits]

mbrkusanin created this revision.
mbrkusanin added reviewers: foad, arsen, rampitec, mshivama.
mbrkusanin added a project: LLVM.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm.
mbrkusanin requested review of this revision.
Herald added a subscriber: wdng.

Split UnalignedAccessMode into UnalignedDSAccess and UnalignedBufferAccess so
that only UnalignedBufferAccess can be enabled by default for AMDHSA


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98491

Files:
  llvm/lib/Target/AMDGPU/AMDGPU.td
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
  llvm/lib/Target/AMDGPU/DSInstructions.td
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
  llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
  llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
  llvm/test/CodeGen/AMDGPU/ds_read2.ll
  llvm/test/CodeGen/AMDGPU/ds_write2.ll
  llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
  llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
  llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
  llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir
  llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline.mir
  llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
  llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D98491.330197.patch
Type: text/x-patch
Size: 31175 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210312/575abad4/attachment.bin>