[llvm] 4d2d585 - [RISCV] Fix up stale VECREDUCE comments. NFC.

[Fraser Cormack via llvm-commits]

Author: Fraser Cormack
Date: 2021-03-12T08:49:46Z
New Revision: 4d2d5855c72909a52ce216e223f21d2dac292c16

URL: https://github.com/llvm/llvm-project/commit/4d2d5855c72909a52ce216e223f21d2dac292c16
DIFF: https://github.com/llvm/llvm-project/commit/4d2d5855c72909a52ce216e223f21d2dac292c16.diff

LOG: [RISCV] Fix up stale VECREDUCE comments. NFC.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D98399

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 51000472c059..3b6fc74b6c82 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2557,9 +2557,6 @@ static unsigned getRVVReductionOp(unsigned ISDOpcode) {
   }
 }
 
-// Take a (supported) standard ISD reduction opcode and transform it to a RISCV
-// reduction opcode. Note that this returns a vector type, which must be
-// further processed to access the scalar result in element 0.
 SDValue RISCVTargetLowering::lowerVECREDUCE(SDValue Op,
                                             SelectionDAG &DAG) const {
   SDLoc DL(Op);
@@ -3634,9 +3631,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
   case ISD::VECREDUCE_UMAX:
   case ISD::VECREDUCE_SMIN:
   case ISD::VECREDUCE_UMIN:
-    // The custom-lowering for these nodes returns a vector whose first element
-    // is the result of the reduction. Extract its first element and let the
-    // legalization for EXTRACT_VECTOR_ELT do the rest of the job.
     if (SDValue V = lowerVECREDUCE(SDValue(N, 0), DAG))
       Results.push_back(V);
     break;