[PATCH] D98479: [RISCV] Add DAG combine to optimize vXi64 all ones/zeros fixed vector on RV32.

[Craig Topper via Phabricator via llvm-commits]

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vXi64 build_vectors are converted to v2Xi32 during type legalization
on RV32. This causes the use of SEW=32 splat instead of SEW=64.

This patch adds a DAG combine to detect the bitcasted pattern
and turn it into a SEW=64 splat.

We could maybe fix this in type legalization, but I'm not sure
we want to lose all zeroes/ones vector knowledge that early since
it's used by negate and not idioms for example.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98479

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

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