nagisa added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll:417
+
+define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
+; RV32-LABEL: test_urem_vec:
----------------
craig.topper wrote:
> nagisa wrote:
> > craig.topper wrote:
> > > nagisa wrote:
> > > > craig.topper wrote:
> > > > > Fixed size vectors on RISCV are scalarized unless you pass a value to -riscv-v-vector-bits-min command line option. Enabling the V extension by itself is not sufficient.
> > > > Ah, I see! Unfortunately enabling the option causes the backend to assert today :(
> > > >
> > > > I'll file some bug reports.
> > > We don't support fixed vector arguments or returns yet either. There's an open patch for it. Loads/store of vectors should work.
> > I ended up filing https://bugs.llvm.org/show_bug.cgi?id=49549
> >
> > (and https://bugs.llvm.org/show_bug.cgi?id=49550)
> >
> > ---
> >
> > Besides that do you have any suggestions on how to best proceed here? I could remove or comment out the test case that involves vectors for now, but it is not clear to me if that's the best way forward.
> Can you use something like this?
>
> ```
> define void @test_urem_vec(<3 x i11>* %X) nounwind {
> %a = load <3 x i11>, <3 x i11>* %X
> %urem = urem <3 x i11> %a, <i11 6, i11 7, i11 -5>
> %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
> %ext = sext <3 x i1> %cmp to <3 x i11>
> store <3 x i11> %ext, <3 x i11>* %X
> ret void
> }
> ```
Yes, that works! Thanks!
Repository:
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CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D98339/new/
https://reviews.llvm.org/D98339