[PATCH] D98310: [RISCV] Support extract_vector_elt for fixed and scalable masked registers.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG9c841cb8e883: [RISCV] Support extract_vector_elt for fixed and scalable masked registers. (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98310/new/

https://reviews.llvm.org/D98310

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

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