[llvm] 0e0c7ef - AMDGPU/GlobalISel: Add more tests for byval arguments
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 11 07:23:15 PST 2021
Author: Matt Arsenault
Date: 2021-03-11T10:23:08-05:00
New Revision: 0e0c7ef8e48ce4b42b5ebb8b71b492280eb91419
URL: https://github.com/llvm/llvm-project/commit/0e0c7ef8e48ce4b42b5ebb8b71b492280eb91419
DIFF: https://github.com/llvm/llvm-project/commit/0e0c7ef8e48ce4b42b5ebb8b71b492280eb91419.diff
LOG: AMDGPU/GlobalISel: Add more tests for byval arguments
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
index c5befb88c782..c33b053bc37a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
@@ -1803,6 +1803,179 @@ define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval(i32) %arg0, i
ret void
}
+define void @void_func_byval_i8_align32_i16_align64(i8 addrspace(5)* byval(i8) %arg0, i16 addrspace(5)* byval(i16) align 64 %arg1) #0 {
+ ; CHECK-LABEL: name: void_func_byval_i8_align32_i16_align64
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $sgpr30_sgpr31
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5)
+ ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p1) = COPY [[C]](p1)
+ ; CHECK: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p5) :: (dereferenceable load 1 from %ir.arg0, addrspace 5)
+ ; CHECK: [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[LOAD1]](p5) :: (dereferenceable load 2 from %ir.arg1, addrspace 5)
+ ; CHECK: G_STORE [[LOAD2]](s8), [[C]](p1) :: (store 1 into `i8 addrspace(1)* null`, addrspace 1)
+ ; CHECK: G_STORE [[LOAD3]](s16), [[COPY1]](p1) :: (store 2 into `i16 addrspace(1)* null`, addrspace 1)
+ ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
+ ; CHECK: S_SETPC_B64_return [[COPY2]]
+ %arg0.load = load i8, i8 addrspace(5)* %arg0
+ %arg1.load = load i16, i16 addrspace(5)* %arg1
+ store i8 %arg0.load, i8 addrspace(1)* null
+ store i16 %arg1.load, i16 addrspace(1)* null
+ ret void
+}
+
+; Make sure the alignment is taken from the correct parameter.
+define void @byval_3ai32_align128_byval_i16_align64([3 x i32] addrspace(5)* byval([3 x i32]) align 128 %arg0, i16 addrspace(5)* byval(i16) align 64 %arg1) #0 {
+ ; CHECK-LABEL: name: byval_3ai32_align128_byval_i16_align64
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $sgpr30_sgpr31
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5)
+ ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, align 16, addrspace 5)
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p1) = COPY [[C]](p1)
+ ; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p5) :: (dereferenceable load 4 from %ir.arg0, addrspace 5)
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[LOAD]], [[C1]](s32)
+ ; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (dereferenceable load 4 from %ir.arg0 + 4, addrspace 5)
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[LOAD]], [[C2]](s32)
+ ; CHECK: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (dereferenceable load 4 from %ir.arg0 + 8, addrspace 5)
+ ; CHECK: [[LOAD5:%[0-9]+]]:_(s16) = G_LOAD [[LOAD1]](p5) :: (dereferenceable load 2 from %ir.arg1, addrspace 5)
+ ; CHECK: G_STORE [[LOAD2]](s32), [[C]](p1) :: (store 4 into `[3 x i32] addrspace(1)* null`, addrspace 1)
+ ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[C]], [[C3]](s64)
+ ; CHECK: G_STORE [[LOAD3]](s32), [[PTR_ADD2]](p1) :: (store 4 into `[3 x i32] addrspace(1)* null` + 4, addrspace 1)
+ ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[C]], [[C4]](s64)
+ ; CHECK: G_STORE [[LOAD4]](s32), [[PTR_ADD3]](p1) :: (store 4 into `[3 x i32] addrspace(1)* null` + 8, addrspace 1)
+ ; CHECK: G_STORE [[LOAD5]](s16), [[COPY1]](p1) :: (store 2 into `i16 addrspace(1)* null`, addrspace 1)
+ ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
+ ; CHECK: S_SETPC_B64_return [[COPY2]]
+ %arg0.load = load [3 x i32], [3 x i32] addrspace(5)* %arg0
+ %arg1.load = load i16, i16 addrspace(5)* %arg1
+ store [3 x i32] %arg0.load, [3 x i32] addrspace(1)* null
+ store i16 %arg1.load, i16 addrspace(1)* null
+ ret void
+}
+
+; byval argument after non-byval stack passed argument
+define void @void_func_v32i32_i32_byval_i8(<32 x i32> %arg0, i32 %arg1, i8 addrspace(5)* byval(i8) %arg2) #0 {
+ ; CHECK-LABEL: name: void_func_v32i32_i32_byval_i8
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $sgpr30_sgpr31
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
+ ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
+ ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
+ ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8
+ ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9
+ ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10
+ ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11
+ ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12
+ ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
+ ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
+ ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
+ ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr16
+ ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr17
+ ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr18
+ ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr19
+ ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr20
+ ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr21
+ ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr22
+ ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr23
+ ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
+ ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
+ ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
+ ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
+ ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
+ ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
+ ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
+ ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5)
+ ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
+ ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
+ ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[C]](p1)
+ ; CHECK: G_STORE [[LOAD]](s32), [[C]](p1) :: (store 4 into `i32 addrspace(1)* null`, addrspace 1)
+ ; CHECK: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[LOAD1]](p5) :: (dereferenceable load 1 from %ir.arg2, addrspace 5)
+ ; CHECK: G_STORE [[LOAD2]](s8), [[COPY33]](p1) :: (store 1 into `i8 addrspace(1)* null`, addrspace 1)
+ ; CHECK: [[COPY34:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
+ ; CHECK: S_SETPC_B64_return [[COPY34]]
+ store i32 %arg1, i32 addrspace(1)* null
+ %arg2.load = load i8, i8 addrspace(5)* %arg2
+ store i8 %arg2.load, i8 addrspace(1)* null
+ ret void
+}
+
+; byval argument before non-byval stack passed argument
+define void @void_func_v32i32_byval_i8_i32(<32 x i32> %arg0, i8 addrspace(5)* byval(i8) %arg1, i32 %arg2) #0 {
+ ; CHECK-LABEL: name: void_func_v32i32_byval_i8_i32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $sgpr30_sgpr31
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
+ ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
+ ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
+ ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr8
+ ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr9
+ ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr10
+ ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11
+ ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr12
+ ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
+ ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
+ ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
+ ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr16
+ ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr17
+ ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr18
+ ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr19
+ ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr20
+ ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr21
+ ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr22
+ ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr23
+ ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr24
+ ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
+ ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
+ ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
+ ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
+ ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
+ ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
+ ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5)
+ ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
+ ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+ ; CHECK: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
+ ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[C]](p1)
+ ; CHECK: G_STORE [[LOAD1]](s32), [[C]](p1) :: (store 4 into `i32 addrspace(1)* null`, addrspace 1)
+ ; CHECK: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p5) :: (dereferenceable load 1 from %ir.arg1, addrspace 5)
+ ; CHECK: G_STORE [[LOAD2]](s8), [[COPY33]](p1) :: (store 1 into `i8 addrspace(1)* null`, addrspace 1)
+ ; CHECK: [[COPY34:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
+ ; CHECK: S_SETPC_B64_return [[COPY34]]
+ store i32 %arg2, i32 addrspace(1)* null
+ %arg1.load = load i8, i8 addrspace(5)* %arg1
+ store i8 %arg1.load, i8 addrspace(1)* null
+ ret void
+}
+
define void @void_func_v32i32_i32_i64(<32 x i32> %arg0, i32 %arg1, i64 %arg2) #0 {
; CHECK-LABEL: name: void_func_v32i32_i32_i64
; CHECK: bb.1 (%ir-block.0):
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