[PATCH] D98372: [RISCV] Handle vmv.x.s intrinsic for i64 vectors on RV32.

Thu Mar 11 02:14:27 PST 2021

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

LGTM. My other question is more about potential future improvements.

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Comment at: llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll:243
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
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I was wondering, given that we need to move 32 into a vector register with a separate instruction, would it potentially be better to use an e32 vslidedown by 1? Not sure how `vsetvli + vslidedown` vs `add + vsrl` stacks up in terms of performance.

Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D98372