[llvm] 478317f - [RISCV] Make the hasStdExtM() check in RISCVInstrInfo::getVLENFactoredAmount emit a diagnostic rather than an assert.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-03-09T08:50:02-08:00
New Revision: 478317fbb79034694df934900665f363dd6c9a70

URL: https://github.com/llvm/llvm-project/commit/478317fbb79034694df934900665f363dd6c9a70
DIFF: https://github.com/llvm/llvm-project/commit/478317fbb79034694df934900665f363dd6c9a70.diff

LOG: [RISCV] Make the hasStdExtM() check in RISCVInstrInfo::getVLENFactoredAmount emit a diagnostic rather than an assert.

As far as I know we're not enforcing the StdExtM must be enabled
to use the V extension. If we use an assert here and hit this
code in a release build we'll silently emit an invalid instruction.

By using a diagnostic we report the error to the user in release
builds. I think there may still be a later fatal error from
the code emitter though.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97970

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfo.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 1956e028d1d0..5e1be68b4835 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1196,8 +1196,10 @@ Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
     BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VN)
         .addReg(RISCV::X0)
         .addImm(NumOfVReg);
-    assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtM() &&
-           "M-extension must be enabled to calculate the vscaled size/offset.");
+    if (!MF.getSubtarget<RISCVSubtarget>().hasStdExtM())
+      MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
+          MF.getFunction(),
+          "M-extension must be enabled to calculate the vscaled size/offset."});
     BuildMI(MBB, II, DL, TII->get(RISCV::MUL), FactorRegister)
         .addReg(SizeOfVector, RegState::Kill)
         .addReg(VN, RegState::Kill);

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 0c6fdce39b82..64f6c6236453 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -15,6 +15,7 @@
 
 #include "RISCVRegisterInfo.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/IR/DiagnosticInfo.h"
 
 #define GET_INSTRINFO_HEADER
 #include "RISCVGenInstrInfo.inc"