[PATCH] D98266: [AMDGPU] Refactor AMDGPUTargetStreamer::EmitCodeEnd

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: rampitec, kzhuravl, msearles.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, arsenm.
foad requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Refactor and add comments to explain where the magic numbers come from
in terms of the instruction cache line size. NFC.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98266

Files:
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp


Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
@@ -264,15 +264,21 @@
   const uint32_t Encoded_s_code_end = 0xbf9f0000;
   const uint32_t Encoded_s_nop = 0xbf800000;
   uint32_t Encoded_pad = Encoded_s_code_end;
-  unsigned FillSize = 48;
+
+  // Instruction cache line size in bytes.
+  const unsigned Log2CacheLineSize = 6;
+  const unsigned CacheLineSize = 1u << Log2CacheLineSize;
+
+  // Enough padding to support prefetch mode 3.
+  unsigned FillSize = 3 * CacheLineSize;
 
   if (AMDGPU::isGFX90A(STI)) {
     Encoded_pad = Encoded_s_nop;
-    FillSize = 256;
+    FillSize = 16 * CacheLineSize;
   }
 
-  OS << "\t.p2alignl 6, " << Encoded_pad << '\n';
-  OS << "\t.fill " << FillSize << ", 4, " << Encoded_pad << '\n';
+  OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
+  OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
   return true;
 }
 
@@ -641,17 +647,23 @@
   const uint32_t Encoded_s_code_end = 0xbf9f0000;
   const uint32_t Encoded_s_nop = 0xbf800000;
   uint32_t Encoded_pad = Encoded_s_code_end;
-  unsigned FillSize = 48;
+
+  // Instruction cache line size in bytes.
+  const unsigned Log2CacheLineSize = 6;
+  const unsigned CacheLineSize = 1u << Log2CacheLineSize;
+
+  // Enough padding to support prefetch mode 3.
+  unsigned FillSize = 3 * CacheLineSize;
 
   if (AMDGPU::isGFX90A(STI)) {
     Encoded_pad = Encoded_s_nop;
-    FillSize = 256;
+    FillSize = 16 * CacheLineSize;
   }
 
   MCStreamer &OS = getStreamer();
   OS.PushSection();
-  OS.emitValueToAlignment(64, Encoded_pad, 4);
-  for (unsigned I = 0; I < FillSize; ++I)
+  OS.emitValueToAlignment(CacheLineSize, Encoded_pad, 4);
+  for (unsigned I = 0; I < FillSize; I += 4)
     OS.emitInt32(Encoded_pad);
   OS.PopSection();
   return true;


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