[PATCH] D98174: [MCA] Add tests for IPC on Cortex-A55

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added a comment.

In D98174#2613940 <https://reviews.llvm.org/D98174#2613940>, @asavonic wrote:

> In D98174#2613867 <https://reviews.llvm.org/D98174#2613867>, @andreadb wrote:
>
>> One last question.
>> What is the plan with the SDIV test cases? I don't think that there is anything that we can do to improve that simulation, since it would require knowledge that isn't available at simulation time. The risk is to end up with a test which isn't very useful in practice (it will always be marked as XFAIL). In which case, I suggest to remove those DIV tests entirely.
>
> They are not very useful as "tests", I agree, but they can be useful as a documentation, 
> highlighting the cases where MCA and hardware do not match. Although there is no point
> in having two tests for the same issue, so we can remove one of them.

True.
However, to be fair, the "issue" (so to say) is in the write definition from the Cortex-A55 scheduling model.
So, the scheduling model file is probably a better place where to document the issue about the DIV latency.
That being said, I don't really have a strong opinion on this, so it is fine by me if you want to still keep one of those tests.


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