[llvm] 0875c2f - [X86][AMX] Add test case for combining AMX bitcast.

via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 9 03:48:22 PST 2021


Author: Luo, Yuanke
Date: 2021-03-09T19:48:01+08:00
New Revision: 0875c2f7f6d60be96fa272c7b1edc15d57dd4f37

URL: https://github.com/llvm/llvm-project/commit/0875c2f7f6d60be96fa272c7b1edc15d57dd4f37
DIFF: https://github.com/llvm/llvm-project/commit/0875c2f7f6d60be96fa272c7b1edc15d57dd4f37.diff

LOG: [X86][AMX] Add test case for combining AMX bitcast.

Added: 
    llvm/test/Transforms/InstCombine/X86/x86-amx.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/X86/x86-amx.ll b/llvm/test/Transforms/InstCombine/X86/x86-amx.ll
new file mode 100644
index 000000000000..254f3c15bc44
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/X86/x86-amx.ll
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S < %s | FileCheck %s
+; RUN: opt -passes=instcombine -S < %s | FileCheck %s
+
+define linkonce_odr dso_local void @foo(<256 x i32>* %arrayidx16, <256 x i32>* %arrayidx29, <256 x i32>* %arrayidx35) local_unnamed_addr {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[FOR_COND9:%.*]]
+; CHECK:       for.cond9:
+; CHECK-NEXT:    br i1 undef, label [[FOR_BODY14:%.*]], label [[EXIT:%.*]]
+; CHECK:       for.body14:
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast <256 x i32>* [[ARRAYIDX16:%.*]] to x86_amx*
+; CHECK-NEXT:    [[T51:%.*]] = load x86_amx, x86_amx* [[TMP0]], align 64
+; CHECK-NEXT:    br label [[FOR_COND18:%.*]]
+; CHECK:       for.cond18:
+; CHECK-NEXT:    [[TMP1:%.*]] = phi x86_amx [ [[T51]], [[FOR_BODY14]] ], [ [[T11:%.*]], [[FOR_BODY24:%.*]] ]
+; CHECK-NEXT:    br i1 undef, label [[FOR_BODY24]], label [[FOR_COND_CLEANUP23:%.*]]
+; CHECK:       for.cond.cleanup23:
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast x86_amx [[TMP1]] to <256 x i32>
+; CHECK-NEXT:    store <256 x i32> [[TMP2]], <256 x i32>* [[ARRAYIDX16]], align 64
+; CHECK-NEXT:    br label [[FOR_COND9]]
+; CHECK:       for.body24:
+; CHECK-NEXT:    [[T6:%.*]] = load <256 x i32>, <256 x i32>* [[ARRAYIDX29:%.*]], align 64
+; CHECK-NEXT:    [[T7:%.*]] = load <256 x i32>, <256 x i32>* [[ARRAYIDX35:%.*]], align 64
+; CHECK-NEXT:    [[T9:%.*]] = bitcast <256 x i32> [[T6]] to x86_amx
+; CHECK-NEXT:    [[T10:%.*]] = bitcast <256 x i32> [[T7]] to x86_amx
+; CHECK-NEXT:    [[T11]] = call x86_amx @llvm.x86.tdpbssd.internal(i16 1, i16 4, i16 4, x86_amx [[TMP1]], x86_amx [[T9]], x86_amx [[T10]])
+; CHECK-NEXT:    br label [[FOR_COND18]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %for.cond9
+for.cond9:                                        ; preds = %for.cond, %for.cond.cleanup23
+  br i1 undef, label %for.body14, label %exit
+
+for.body14:
+  %t5 = load <256 x i32>, <256 x i32>* %arrayidx16, align 64
+  br label %for.cond18
+
+for.cond18:                                       ; preds = %for.body24, %for.body14
+  %sub_c.sroa.0.0 = phi <256 x i32> [ %t5, %for.body14 ], [ %t12, %for.body24 ]
+  br i1 undef, label %for.body24, label %for.cond.cleanup23
+
+for.cond.cleanup23:                               ; preds = %for.cond18
+  store <256 x i32> %sub_c.sroa.0.0, <256 x i32>* %arrayidx16, align 64
+  br label %for.cond9
+
+for.body24:                                       ; preds = %for.cond18
+  %t6 = load <256 x i32>, <256 x i32>* %arrayidx29, align 64
+  %t7 = load <256 x i32>, <256 x i32>* %arrayidx35, align 64
+  %t8 = bitcast <256 x i32> %sub_c.sroa.0.0 to x86_amx
+  %t9 = bitcast <256 x i32> %t6 to x86_amx
+  %t10 = bitcast <256 x i32> %t7 to x86_amx
+  %t11 = call x86_amx @llvm.x86.tdpbssd.internal(i16 1, i16 4, i16 4, x86_amx %t8, x86_amx %t9, x86_amx %t10) #12
+  %t12 = bitcast x86_amx %t11 to <256 x i32>
+  br label %for.cond18
+
+exit:
+  ret void
+}
+
+declare x86_amx @llvm.x86.tileloadd64.internal(i16, i16, i8*, i64)
+declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
+declare void @llvm.x86.tilestored64.internal(i16, i16, i8*, i64, x86_amx)


        


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