[PATCH] D98185: [RISCV][MC] Fix nf encoding for vector ld/st whole register

[ShihPo Hung via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5cdb2e98608b: [RISCV][MC] Fix nf encoding for vector ld/st whole register (authored by arcbbb).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98185/new/

https://reviews.llvm.org/D98185

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/aliases.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/store.s

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