[PATCH] D98185: [RISCV][MC] Fix nf encoding for vector ld/st whole register

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a subscriber: Paul-C-Anagnostopoulos.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM. Does this need to be merged to LLVM 12? If so please file a bugzilla.



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:514
-defm VL4R : VWholeLoad<4, "vl4r", VRM4>;
-defm VL8R : VWholeLoad<8, "vl8r", VRM8>;
 def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>;
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Feels like tablegen should have maybe warned about the int being truncated to 3 bits. @Paul-C-Anagnostopoulos?


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  https://reviews.llvm.org/D98185/new/

https://reviews.llvm.org/D98185