[PATCH] D98185: [RISCV][MC] Fix nf encoding for vector ld/st whole register

[ShihPo Hung via Phabricator via llvm-commits]

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The three bit nf is one less than the number of NFIELDS,
so we manually decrement 1 for VS1/2/4/8R & VL1/2/4/8R.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98185

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/aliases.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/store.s

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