[PATCH] D98180: [RISCV] Fix vector load/store whole register inst encoding

[Fraser Cormack via Phabricator via llvm-commits]

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The `nf` field of the RVV vector load/store whole register instructions
(Section 7.9) "encodes the number of vector registers to transfer,
numbered successively after the base". Or, the log2 of the number of
registers to transfer. We were previously encoding it naively as
1/2/4/8, the last of which doesn't even fit in the 3-bit field.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98180

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/aliases.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/store.s

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