[PATCH] D97954: [RISCV] Support fixed-length vectors in the calling convention
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 8 01:41:43 PST 2021
frasercrmck marked an inline comment as done.
frasercrmck added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4539
// Any return value split in to more than two values can't be returned
- // directly.
- if (IsRet && ValNo > 1)
+ // directly. Vectors are returned via the avaiable vector registers.
+ if (!LocVT.isVector() && IsRet && ValNo > 1)
----------------
craig.topper wrote:
> avaiable->available
Fixed, cheers.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D97954/new/
https://reviews.llvm.org/D97954
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