[PATCH] D98159: [RISCV] Add RISCVISD::BR_CC similar to RISCVISD::SELECT_CC.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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This allows me to introduce similar combines for branches as
we have recently added for SELECT_CC. Some of them are less
useful for standalone setccs and only help branch instructions.
By having a BR_CC node its easier to only affect branches.

I'm using CondCodeSDNode to make isel patterns easier to
write so we can refer to the codes by name. SELECT_CC uses a
constant instead.

I've normalizing the condition code just like SELECT_CC so
we need less patterns for the swapped conditions. I've also
folded the setlt X, -1 handling into the normalize to get rid
of that special case isel pattern.

computeKnownBitsForTargetNode support for SELECT_CC is added
to allow MaskedValueIsZero to work for cases where the true
and false values of the SELECT_CC are setccs and the
result of the SELECT_CC is used by a BR_CC. This was needed
to avoid regressions in some of the overflow tests.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98159

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/xaluo.ll

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