[llvm] 772a501 - [X86] canonicalizeShuffleWithBinOps - shuffle oneuse constants.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-03-07T11:17:03Z
New Revision: 772a501bf41fd15294192b9522c4567a9fc25834

URL: https://github.com/llvm/llvm-project/commit/772a501bf41fd15294192b9522c4567a9fc25834
DIFF: https://github.com/llvm/llvm-project/commit/772a501bf41fd15294192b9522c4567a9fc25834.diff

LOG: [X86] canonicalizeShuffleWithBinOps - shuffle oneuse constants.

We can freely shuffle all ones/zeros constants but we can also freely shuffle other constants as long as they only have one use.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/promote-cmp.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 039ddc3e76f1..4ea79a4668ae 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36819,12 +36819,15 @@ static SDValue canonicalizeShuffleWithBinOps(SDValue N, SelectionDAG &DAG,
   EVT ShuffleVT = N.getValueType();
 
   auto IsMergeableWithShuffle = [](SDValue Op) {
-    // AllZeros/AllOnes constants are freely shuffled.
+    // AllZeros/AllOnes constants are freely shuffled and will peek through bitcasts.
+    // Other constant build vectors do not peek through bitcasts.
     return ISD::isBuildVectorAllOnes(Op.getNode()) ||
-           ISD::isBuildVectorAllZeros(Op.getNode());
+           ISD::isBuildVectorAllZeros(Op.getNode()) ||
+           ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) ||
+           ISD::isBuildVectorOfConstantFPSDNodes(Op.getNode());
   };
   auto IsSafeToMoveShuffle = [ShuffleVT](SDValue Op, unsigned BinOp) {
-    // Ensure we only shuffle whole vector src elements, unless its logical
+    // Ensure we only shuffle whole vector src elements, unless its a logical
     // binops where we can more aggressively move shuffles from dst to src.
     return BinOp == ISD::AND || BinOp == ISD::OR || BinOp == ISD::XOR ||
            (Op.getScalarValueSizeInBits() <= ShuffleVT.getScalarSizeInBits());
@@ -36840,8 +36843,8 @@ static SDValue canonicalizeShuffleWithBinOps(SDValue N, SelectionDAG &DAG,
       SDValue N0 = peekThroughOneUseBitcasts(N.getOperand(0));
       unsigned SrcOpcode = N0.getOpcode();
       if (TLI.isBinOp(SrcOpcode) && IsSafeToMoveShuffle(N0, SrcOpcode)) {
-        SDValue Op00 = N0.getOperand(0);
-        SDValue Op01 = N0.getOperand(1);
+        SDValue Op00 = peekThroughOneUseBitcasts(N0.getOperand(0));
+        SDValue Op01 = peekThroughOneUseBitcasts(N0.getOperand(1));
         if (IsMergeableWithShuffle(Op00) || IsMergeableWithShuffle(Op01)) {
           SDValue LHS, RHS;
           Op00 = DAG.getBitcast(ShuffleVT, Op00);

diff  --git a/llvm/test/CodeGen/X86/promote-cmp.ll b/llvm/test/CodeGen/X86/promote-cmp.ll
index c59f808a3029..37450df80941 100644
--- a/llvm/test/CodeGen/X86/promote-cmp.ll
+++ b/llvm/test/CodeGen/X86/promote-cmp.ll
@@ -28,7 +28,6 @@ define <4 x i64> @PR45808(<4 x i64> %0, <4 x i64> %1) {
 ; SSE2-NEXT:    shufps {{.*#+}} xmm5 = xmm5[1,3],xmm8[1,3]
 ; SSE2-NEXT:    orps %xmm4, %xmm5
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[2,1,3,3]
-; SSE2-NEXT:    pxor {{.*}}(%rip), %xmm5
 ; SSE2-NEXT:    psllq $63, %xmm4
 ; SSE2-NEXT:    psrad $31, %xmm4
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
@@ -36,6 +35,7 @@ define <4 x i64> @PR45808(<4 x i64> %0, <4 x i64> %1) {
 ; SSE2-NEXT:    pandn %xmm3, %xmm4
 ; SSE2-NEXT:    por %xmm4, %xmm1
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm5[0,1,1,3]
+; SSE2-NEXT:    pxor {{.*}}(%rip), %xmm3
 ; SSE2-NEXT:    psllq $63, %xmm3
 ; SSE2-NEXT:    psrad $31, %xmm3
 ; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]