[PATCH] D98101: [RISCV] Enable the LocalStackSlotAllocation pass support
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 5 22:20:33 PST 2021
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:291
+ // For RISC-V, The machine instructions that include a FrameIndex operand
+ // are load/store(exclude vector load/store), ADDI instructions.
+ if (!MI->mayLoad() && !MI->mayStore() && !(MI->getOpcode() == RISCV::ADDI))
----------------
StephenFan wrote:
> craig.topper wrote:
> > I think vector load/store can have a frameindex operand. There's no immediate field so it will get split out into an ADDI in eliminateFrameIndex, but I think that happens later.
> In the RISCVIselDAGToDAG.cpp:
> ```
> case ISD::FrameIndex: {
> SDValue Imm = CurDAG->getTargetConstant(0, DL, XLenVT);
> int FI = cast<FrameIndexSDNode>(Node)->getIndex();
> SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
> ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm));
> return;
> }
> ```
> So the llvm ir like this :
> ```
> %addr = alloca i8
> call void callee(i8* %addr)
> ```
> the %addr will be selected to ADDI
Right. I was just asking why the comment says vector load/store are different?
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https://reviews.llvm.org/D98101/new/
https://reviews.llvm.org/D98101
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