[PATCH] D98100: [mir] Change 'undef' for MMO base addresses to 'unknown-address'
Daniel Sanders via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 5 20:47:58 PST 2021
dsanders created this revision.
dsanders added a reviewer: qcolombet.
Herald added subscribers: kerbowa, pengfei, hiraditya, nhaehnle, jvesely, nemanjai.
dsanders requested review of this revision.
Herald added a project: LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D98100
Files:
llvm/lib/CodeGen/MIRParser/MILexer.cpp
llvm/lib/CodeGen/MIRParser/MILexer.h
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/lib/CodeGen/MachineOperand.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
llvm/test/CodeGen/MIR/AArch64/base-memoperands.mir
llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-undef.mir
llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
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