[PATCH] D98053: [mac/lld] Fix scale computation for vector ops in PAGEOFF12 relocations

Fri Mar 5 12:59:56 PST 2021

thakis added inline comments.

================
Comment at: lld/MachO/Arch/ARM64.cpp:134
+    scale = base >> 30;
+    if (scale == 0 && (base & 0x0480'0000) == 0x0480'0000) // vector op?
+      scale = 4;
----------------
int3 wrote:
> smeenai wrote:
> > If I'm reading the encoding table right (downloaded from https://developer.arm.com/documentation/ddi0487/ga/), then yup, this means a 128-bit operation.
> I interpreted the question mark as "here we are checking if we have a vector op", not "I'm not entirely sure this is a vector op"... but I guess it's a bit confusing since line 132 doesn't have a question mark
Yes, that's how I meant it. This is "C7.2.191 LDR (immediate, SIMD&FP)" in the ARM ARM, "128-bit variant Applies when size == 00 && opc == 11."

I have to say I find https://developer.arm.com/documentation/ddi0487/ga/ pretty hard to read though. I ended up writing myself a decoder (first few lines of https://github.com/nico/mra_tools) to help me navigate that PDF. Maybe there's some easier way to answer "given 32-bit aarch64 instruction, find out what exactly it means", but that script works for me now that I've written it :)

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98053/new/

https://reviews.llvm.org/D98053