[PATCH] D97828: [LoopInterchange] Disallow interchange when memory accesses are guarded by control flow (PR48057)

[Ta-Wei Tu via Phabricator via llvm-commits]

TaWeiTu added a comment.

The following test in `lcssa.ll` is failing:

  define void @lcssa_05(i32* %ptr) {
  entry:
    br label %outer.header
  
  outer.header:                                     ; preds = %outer.inc, %entry
    %iv.outer = phi i64 [ 1, %entry ], [ %iv.outer.next, %outer.inc ]
    br label %for.body3
  
  for.body3:                                        ; preds = %bb3, %outer.header
    %iv.inner = phi i64 [ %iv.inner.next, %bb3 ], [ 1, %outer.header ]
    br i1 undef, label %bb2, label %bb3
  
  bb2:                                              ; preds = %for.body3
    %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @A, i64 0, i64 %iv.inner, i64 %iv.outer
    %vA = load i32, i32* %arrayidx5
    %arrayidx9 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 x i32]]* @C, i64 0, i64 %iv.inner, i64 %iv.outer
    %vC = load i32, i32* %arrayidx9
    %add = add nsw i32 %vA, %vC
    br label %bb3
  
  bb3:                                              ; preds = %bb2, %for.body3
    %addp = phi i32 [ %add, %bb2 ], [ 0, %for.body3 ]
    store i32 %addp, i32* %ptr
    %iv.inner.next = add nuw nsw i64 %iv.inner, 1
    %exitcond = icmp eq i64 %iv.inner.next, 100
    br i1 %exitcond, label %outer.inc, label %for.body3
  
  outer.inc:                                        ; preds = %bb3
    %iv.inner.lcssa = phi i64 [ %iv.inner, %bb3 ]
    %iv.outer.next = add nsw i64 %iv.outer, 1
    %cmp = icmp eq i64 %iv.outer.next, 100
    br i1 %cmp, label %outer.header, label %for.exit
  
  for.exit:                                         ; preds = %outer.inc
    %iv.inner.lcssa.lcssa = phi i64 [ %iv.inner.lcssa, %outer.inc ]
    store i64 %iv.inner.lcssa.lcssa, i64* @Y
    br label %for.end16
  
  for.end16:                                        ; preds = %for.exit
    ret void
  }

The test is expecting the loops to be interchanged, but judging from `br i1 undef, label %bb2, label %bb3` I think the interchange should probabily be considered invalid in this case?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97828/new/

https://reviews.llvm.org/D97828