[PATCH] D97609: [RISCV] Add support for VECTOR_REVERSE for scalable vector types.

[Zakk Chen via Phabricator via llvm-commits]

khchen added a comment.

Overall LGTM, waiting for @frasercrmck's comment.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1496
+    // (0, 1,..., VLMAX-2, VLMAX-1) -> (VLMAX-1, VLMAX-2,..., 1, 0).
+    // FIXME: This implementation doesn't work for vectors of more than 256
+    // elements for SEW==8.
----------------
craig.topper wrote:
> frasercrmck wrote:
> > I suppose we'll have to promote to i16 for this case?
> Yeah, but we don't really have a good way of know if it is needed without just always doing it or deciding based on whether -riscv-vector-bits-max is set and what its value is?
> 
> We also can't promote to i16 without splitting for lmul=8.
Agree, it's really a problem, unfortunately vrgatherei16 can not support i8m8 case directly.

I think maybe compiler could emit a warning for non-workable case if user specific `-riscv-vector-bits-max`.


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https://reviews.llvm.org/D97609