[PATCH] D98013: [AMDGPU] Do not attempt sgpr spills to vgpr, when it is disabled

[Venkata Ramanaiah Nalamothu via Phabricator via llvm-commits]

RamNalamothu created this revision.
RamNalamothu added reviewers: kerbowa, arsenm, t-tye, scott.linder.
Herald added subscribers: hiraditya, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, qcolombet.
RamNalamothu requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

This covers a path missed in https://reviews.llvm.org/D95768.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98013

Files:
  llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll


Index: llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
+++ llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
@@ -8,13 +8,19 @@
 ; GCN-LABEL: {{^}}callee_with_stack_and_call:
 ; SPILL-TO-VGPR:      buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
 ; SPILL-TO-VGPR:      v_writelane_b32 v40, s33, 2
+; SPILL-TO-VGPR:      v_writelane_b32 v40, s30, 0
+; SPILL-TO-VGPR:      v_writelane_b32 v40, s31, 1
 ; NO-SPILL-TO-VGPR:   v_mov_b32_e32 v0, s33
 ; NO-SPILL-TO-VGPR:   buffer_store_dword v0, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; NO-SPILL-TO-VGPR:   v_writelane_b32 v1, s30, 0
+; NO-SPILL-TO-VGPR:   v_writelane_b32 v1, s31, 1
+; NO-SPILL-TO-VGPR:   buffer_store_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
 
 ; GCN:                s_swappc_b64 s[30:31], s[4:5]
 
 ; SPILL-TO-VGPR:      v_readlane_b32 s4, v40, 0
 ; SPILL-TO-VGPR:      v_readlane_b32 s5, v40, 1
+; NO-SPILL-TO-VGPR:   buffer_load_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
 ; NO-SPILL-TO-VGPR:   v_readlane_b32 s4, v1, 0
 ; NO-SPILL-TO-VGPR:   v_readlane_b32 s5, v1, 1
 
Index: llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -365,7 +365,7 @@
           }
         }
 
-        if (!TII->isSGPRSpill(MI))
+        if (!TII->isSGPRSpill(MI) || !TRI->spillSGPRToVGPR())
           continue;
 
         int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();


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