[PATCH] D97954: [RISCV] Support fixed-length vectors in the calling convention

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4539
   // Any return value split in to more than two values can't be returned
-  // directly.
-  if (IsRet && ValNo > 1)
+  // directly. Vectors are returned via the avaiable vector registers.
+  if (!LocVT.isVector() && IsRet && ValNo > 1)
----------------
avaiable->available


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97954/new/

https://reviews.llvm.org/D97954