[llvm] a1155ae - [AVR] Fix lifeness issues in the AVR backend
Ayke van Laethem via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 4 05:04:47 PST 2021
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Author: Ayke van Laethem
Date: 2021-03-04T14:04:39+01:00
New Revision: a1155ae64dc7f3672e81ff7db4f58a371d36e9f0
URL: https://github.com/llvm/llvm-project/commit/a1155ae64dc7f3672e81ff7db4f58a371d36e9f0
DIFF: https://github.com/llvm/llvm-project/commit/a1155ae64dc7f3672e81ff7db4f58a371d36e9f0.diff
LOG: [AVR] Fix lifeness issues in the AVR backend
This patch is a large number of small changes that should hopefully not
affect the generated machine code but are still important to get right
so that the machine verifier won't complain about them.
The llvm/test/CodeGen/AVR/pseudo/*.mir changes are also necessary
because without the liveins the used registers are considered undefined
by the machine verifier and it will complain about them.
Differential Revision: https://reviews.llvm.org/D97172
Added:
Modified:
llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
llvm/lib/Target/AVR/AVRFrameLowering.cpp
llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir
llvm/test/CodeGen/AVR/pseudo/COMWRd.mir
llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir
llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir
llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir
llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir
llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir
llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir
llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir
llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
llvm/test/CodeGen/AVR/pseudo/SEXT.mir
llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir
llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir
llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
llvm/test/CodeGen/AVR/pseudo/ZEXT.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
index 8fb020ce9c62..7aebf9a763f5 100644
--- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
@@ -1055,6 +1055,7 @@ bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
Register SrcLoReg, SrcHiReg;
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
+ bool DstIsUndef = MI.getOperand(0).isUndef();
bool SrcIsKill = MI.getOperand(1).isKill();
unsigned OpLo = AVR::STPtrRr;
unsigned OpHi = AVR::STDPtrQRr;
@@ -1062,11 +1063,11 @@ bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
//:TODO: need to reverse this order like inw and stsw?
auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(DstReg)
+ .addReg(DstReg, getUndefRegState(DstIsUndef))
.addReg(SrcLoReg, getKillRegState(SrcIsKill));
auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(DstReg)
+ .addReg(DstReg, getUndefRegState(DstIsUndef))
.addImm(1)
.addReg(SrcHiReg, getKillRegState(SrcIsKill));
@@ -1435,7 +1436,7 @@ bool AVRExpandPseudo::expand<AVR::LSLW4Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstHiReg, getKillRegState(DstIsKill))
- .addReg(DstLoReg, getKillRegState(DstIsKill));
+ .addReg(DstLoReg);
// SREG is implicitly dead.
MI1->getOperand(3).setIsDead();
@@ -1453,7 +1454,7 @@ bool AVRExpandPseudo::expand<AVR::LSLW4Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstHiReg, getKillRegState(DstIsKill))
- .addReg(DstLoReg, getKillRegState(DstIsKill));
+ .addReg(DstLoReg);
if (ImpIsDead)
MI3->getOperand(3).setIsDead();
@@ -1474,7 +1475,7 @@ bool AVRExpandPseudo::expand<AVR::LSLW8Rd>(Block &MBB, BlockIt MBBI) {
// mov Rh, Rl
buildMI(MBB, MBBI, AVR::MOVRdRr)
.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstLoReg, getKillRegState(DstIsKill));
+ .addReg(DstLoReg);
// clr Rl
auto MIBLO =
@@ -1502,7 +1503,7 @@ bool AVRExpandPseudo::expand<AVR::LSLW12Rd>(Block &MBB, BlockIt MBBI) {
// mov Rh, Rl
buildMI(MBB, MBBI, AVR::MOVRdRr)
.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstLoReg, getKillRegState(DstIsKill));
+ .addReg(DstLoReg);
// swap Rh
buildMI(MBB, MBBI, AVR::SWAPRd)
@@ -1595,7 +1596,7 @@ bool AVRExpandPseudo::expand<AVR::LSRW4Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstLoReg, getKillRegState(DstIsKill))
- .addReg(DstHiReg, getKillRegState(DstIsKill));
+ .addReg(DstHiReg);
// SREG is implicitly dead.
MI1->getOperand(3).setIsDead();
@@ -1613,7 +1614,7 @@ bool AVRExpandPseudo::expand<AVR::LSRW4Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstLoReg, getKillRegState(DstIsKill))
- .addReg(DstHiReg, getKillRegState(DstIsKill));
+ .addReg(DstHiReg);
if (ImpIsDead)
MI3->getOperand(3).setIsDead();
@@ -1747,7 +1748,7 @@ bool AVRExpandPseudo::expand<AVR::ASRW8Rd>(Block &MBB, BlockIt MBBI) {
// Move upper byte to lower byte.
buildMI(MBB, MBBI, AVR::MOVRdRr)
.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, getKillRegState(DstIsKill));
+ .addReg(DstHiReg);
// Move the sign bit to the C flag.
buildMI(MBB, MBBI, AVR::ADDRdRr)
@@ -1782,7 +1783,8 @@ bool AVRExpandPseudo::expand<AVR::LSLB7Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::RORRd)
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstReg, getKillRegState(DstIsKill));
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ ->getOperand(3).setIsUndef(true);
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
@@ -1819,7 +1821,8 @@ bool AVRExpandPseudo::expand<AVR::LSRB7Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::ADCRdRr)
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstReg, getKillRegState(DstIsKill))
- .addReg(DstReg, getKillRegState(DstIsKill));
+ .addReg(DstReg, getKillRegState(DstIsKill))
+ ->getOperand(4).setIsUndef(true);
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
@@ -1958,8 +1961,8 @@ template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {
auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
- .addReg(DstHiReg, RegState::Kill)
- .addReg(DstHiReg, RegState::Kill);
+ .addReg(DstHiReg, RegState::Kill | RegState::Undef)
+ .addReg(DstHiReg, RegState::Kill | RegState::Undef);
if (ImpIsDead)
EOR->getOperand(3).setIsDead();
diff --git a/llvm/lib/Target/AVR/AVRFrameLowering.cpp b/llvm/lib/Target/AVR/AVRFrameLowering.cpp
index 757b41466c3f..e99801032037 100644
--- a/llvm/lib/Target/AVR/AVRFrameLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRFrameLowering.cpp
@@ -362,7 +362,7 @@ MachineBasicBlock::iterator AVRFrameLowering::eliminateCallFramePseudoInstr(
New->getOperand(3).setIsDead();
BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
- .addReg(AVR::R31R30, RegState::Kill);
+ .addReg(AVR::R31R30);
// Make sure the remaining stack stores are converted to real store
// instructions.
diff --git a/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
index aa10f6a95e4f..26263991de09 100644
--- a/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
@@ -14,6 +14,7 @@
name: test_adcwrdrr
body: |
bb.0.entry:
+ liveins: $r15r14, $r21r20, $sreg
; CHECK-LABEL: test_adcwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
index a8cd4b425069..1dfa4174d7a8 100644
--- a/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
@@ -14,6 +14,7 @@
name: test_addwrdrr
body: |
bb.0.entry:
+ liveins: $r15r14, $r21r20
; CHECK-LABEL: test_addwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
index 340c7c3d7c46..94d580b9b07a 100644
--- a/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
@@ -14,6 +14,7 @@
name: test_andiwrdrr
body: |
bb.0.entry:
+ liveins: $r17r16
; CHECK-LABEL: test_andiwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
index b3bc6a80067f..98295d06d1e9 100644
--- a/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
@@ -14,6 +14,7 @@
name: test_andwrdrr
body: |
bb.0.entry:
+ liveins: $r15r14, $r21r20
; CHECK-LABEL: test_andwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir b/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir
index e364d8108763..79b6929172d7 100644
--- a/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir
@@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
+ liveins: $r15r14
; CHECK-LABEL: test
diff --git a/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir
index 4718d7d1613f..bd3ce4c821c9 100644
--- a/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir
@@ -14,6 +14,7 @@
name: test_comwrd
body: |
bb.0.entry:
+ liveins: $r15r14
; CHECK-LABEL: test_comwrd
diff --git a/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
index 2ed3d10acef1..d51a757b475a 100644
--- a/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
@@ -14,6 +14,7 @@
name: test_cpcwrdrr
body: |
bb.0.entry:
+ liveins: $r21r20, $r23r22, $sreg
; CHECK-LABEL: test_cpcwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
index 62069a770b4d..bb9f8cbe7423 100644
--- a/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
@@ -14,6 +14,7 @@
name: test_cpwrdrr
body: |
bb.0.entry:
+ liveins: $r15r14, $r21r20
; CHECK-LABEL: test_cpwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir
index 3ff829ae1f68..9ff4e55b15cb 100644
--- a/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir
@@ -14,6 +14,7 @@
name: test_eorwrdrr
body: |
bb.0.entry:
+ liveins: $r15r14, $r21r20
; CHECK-LABEL: test_eorwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir b/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir
index 8815802261e5..f45eeb661dbb 100644
--- a/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir
@@ -18,6 +18,7 @@ registers:
- { id: 0, class: _ }
body: |
bb.0.entry:
+ liveins: $r31r30
; CHECK-LABEL: test
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
index ef8519ed9de4..d13bf118b98d 100644
--- a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
@@ -15,6 +15,7 @@ name: test_lddwrdptrq
tracksRegLiveness: true
body: |
bb.0.entry:
+ liveins: $r31r30
; CHECK-LABEL: test_lddwrdptrq
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
index 3c3a7219ee3e..9ceef4c1bf85 100644
--- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
@@ -15,6 +15,7 @@ name: test_ldwrdptr
tracksRegLiveness: true
body: |
bb.0.entry:
+ liveins: $r31r30
; CHECK-LABEL: test_ldwrdptr
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
index 2343d0df4927..d86b60b97e34 100644
--- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
@@ -14,6 +14,7 @@
name: test_ldwrdptr
body: |
bb.0.entry:
+ liveins: $r31r30
; CHECK-LABEL: test_ldwrdptr
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
index 39abc4590b3d..56623ecd0cac 100644
--- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
@@ -14,6 +14,7 @@
name: test_ldwrdptrpd
body: |
bb.0.entry:
+ liveins: $r31r30
; CHECK-LABEL: test_ldwrdptrpd
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
index 42c255a4da9d..98429a41c1e4 100644
--- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
@@ -14,6 +14,7 @@
name: test_ldwrdptrpi
body: |
bb.0.entry:
+ liveins: $r31r30
; CHECK-LABEL: test_ldwrdptrpi
diff --git a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir
index b260e70e509b..b1b9f1f249bd 100644
--- a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir
@@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
+ liveins: $r15r14
; CHECK-LABEL: test
diff --git a/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir
index d3bee8bb2f5a..d7fabf64d575 100644
--- a/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir
@@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
+ liveins: $r15r14
; CHECK-LABEL: test
diff --git a/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir b/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
index 5cf947e8830a..71ed9a405ffb 100644
--- a/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
@@ -14,6 +14,7 @@
name: test_negwrd
body: |
bb.0.entry:
+ liveins: $r15r14
; CHECK-LABEL: test_negwrd
diff --git a/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir
index 568f8b992158..169e644d5467 100644
--- a/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir
@@ -14,6 +14,7 @@
name: test_oriwrdrr
body: |
bb.0.entry:
+ liveins: $r21r20
; CHECK-LABEL: test_oriwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir
index 6f4167b99bfe..eb2cea6a9c74 100644
--- a/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir
@@ -14,6 +14,7 @@
name: test_orwrdrr
body: |
bb.0.entry:
+ liveins: $r15r14, $r21r20
; CHECK-LABEL: test_orwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir b/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir
index 53ed8cc39799..3152085cd14e 100644
--- a/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir
@@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
+ liveins: $r15r14
; CHECK-LABEL: test
diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
index 8b8c4627010b..303ee1f7f0d7 100644
--- a/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
@@ -14,6 +14,7 @@
name: test_sbciwrdk
body: |
bb.0.entry:
+ liveins: $r21r20, $sreg
; CHECK-LABEL: test_sbciwrdk
diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
index 9fbc6def80b1..4e21ba15028f 100644
--- a/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
@@ -14,6 +14,7 @@
name: test_sbcwrdrr
body: |
bb.0.entry:
+ liveins: $r15r14, $r21r20, $sreg
; CHECK-LABEL: test_sbcwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir
index b7077a3db281..0411673966b1 100644
--- a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir
@@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
+ liveins: $r31
; CHECK-LABEL: test
diff --git a/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir b/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir
index 9302f15800ae..96a648b5622e 100644
--- a/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir
@@ -14,6 +14,7 @@
name: test_stswkrr
body: |
bb.0.entry:
+ liveins: $r31r30
; CHECK-LABEL: test_stswkrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
index c8a5eba7df6d..f255de3b54b4 100644
--- a/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
@@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
+ liveins: $r31r30
; CHECK-LABEL: test
diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
index 3d65cab9bb5b..1f1a199926a0 100644
--- a/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
@@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
+ liveins: $r31r30
; CHECK-LABEL: test
diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir
index 3ed4a50b80b2..203eb6b0401d 100644
--- a/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir
@@ -14,6 +14,7 @@
name: test_stwptrrr
body: |
bb.0.entry:
+ liveins: $r31r30, $r17r16
; CHECK-LABEL: test_stwptrrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
index 3ea833fd2faf..3d1628fcb906 100644
--- a/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
@@ -14,6 +14,7 @@
name: test_subiwrdrr
body: |
bb.0.entry:
+ liveins: $r21r20
; CHECK-LABEL: test_subiwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
index 85036464be5e..30e69abc9e29 100644
--- a/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
@@ -14,6 +14,7 @@
name: test_subwrdrr
body: |
bb.0.entry:
+ liveins: $r21r20, $r15r14
; CHECK-LABEL: test_subwrdrr
diff --git a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir
index b7077a3db281..0411673966b1 100644
--- a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir
@@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
+ liveins: $r31
; CHECK-LABEL: test
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