[PATCH] D96394: [AVR] Improve inline assembly

[Ayke via Phabricator via llvm-commits]

aykevl added a comment.

I don't really understand what you're doing here. For example:

  case 'd': // Upper registers r16..r31.
    if (VT == MVT::i8)
      return std::make_pair(0U, &AVR::LD8RegClass);
    else if (VT == MVT::i16)
      return std::make_pair(0U, &AVR::DLDREGSRegClass);
    break;

If I'm reading https://www.nongnu.org/avr-libc/user-manual/inline_asm.html correctly, this appears to imply an 8-bit register, but you're also implementing support for 16-bit registers. Why?



================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:1918-1921
-  // We only support i8 and i16.
-  //
-  //:FIXME: remove this assert for now since it gets sometimes executed
-  // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
----------------
Why did you remove this assert entirely? It looks like a sensible assert.


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  https://reviews.llvm.org/D96394/new/

https://reviews.llvm.org/D96394