[PATCH] D97842: [RISCV] Preserve fixed-length VL on insert_vector_elt in more cases

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll:13
 ; RV32-NEXT:    vle64.v v26, (a0)
 ; RV32-NEXT:    vsetvli a3, zero, e64,m2,ta,mu
 ; RV32-NEXT:    vmv.v.x v28, a2
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craig.topper wrote:
> frasercrmck wrote:
> > Still using VLMAX here, because we're splatting an i64 using the vector container type. I suppose we either need a custom node or must emit something in the fixed-length type and converting back to the scalable type. I tried that with build_vector and splat_vector but neither worked. build_vector expanded itself, and splat_vector doesn't work on fixed-length vectors (and I'm not sure we want to).
> > 
> > Do you have any ideas, @craig.topper? 
> Nothing great beyond replicating the sequence in lowerSPLATVECTOR using RISCVISD::*_VL nodes. 
> 
> I'm looking at type legalizing the vmv_v_x intrinsic for i64 on RV32 which has the same problem.
Yeah, perhaps that's just what we'll have to do. As a free function to emit the sequence in place? Because I believe build_vector automatically legalizes itself in an unhelpful way, and splat_vector could potentially open up a can of worms?


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