[PATCH] D97280: [AArch64] Extend vecreduce -> udot handling to mla reductions

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer accepted this revision.
SjoerdMeijer added a comment.
This revision is now accepted and ready to land.

Looks okay to me.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11756
+  if (ExtOpcode == ISD::MUL) {
+    A = Op0.getOperand(0);
+    B = Op0.getOperand(1);
----------------
Nit: can we not do:

  Op0 = Op0.getOperand(0);

to avoid creating As and Bs?


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https://reviews.llvm.org/D97280